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  4. Electro-thermal co-design of chip-package-board systems
 
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2013
Conference Paper
Title

Electro-thermal co-design of chip-package-board systems

Abstract
We propose an innovative thermal modeling approach that takes into account different "levels-of-knowledge" as they become available during the design phases of microelectronic systems. There are many tools available for thermal simulations which are well-suited for high-precision modeling. However, their applicability severely diminishes if CAD models are not available or modeling time is limited. Especially for electro-thermal co-design, where several spins between modeling and simulation are required, modeling time quickly becomes prohibitively large. By a combination of different techniques our solution offers fast and intuitive modeling, continuous addition of detail, very short simulation times, and open interfaces. In this paper we present our thermal modeling approach based on constructive solid geometry (CSG). We discuss advantages and limits of this solution and demonstrate its performance on an example of industrially-relevant complexity.
Author(s)
Sohrmann, Christoph  
Fraunhofer-Institut für Integrierte Schaltungen IIS  
Heinig, Andy  
Fraunhofer-Institut für Integrierte Schaltungen IIS  
Dittrich, Michael
Fraunhofer-Institut für Integrierte Schaltungen IIS  
Jancke, Roland  
Fraunhofer-Institut für Integrierte Schaltungen IIS  
Schneider, Peter  
Fraunhofer-Institut für Integrierte Schaltungen IIS  
Mainwork
19th International Workshop on Thermal Investigations of ICs and Systems, THERMINIC 2013  
Conference
International Workshop on Thermal Investigations of ICs and Systems (THERMINIC) 2013  
Open Access
File(s)
Download (802 KB)
Rights
Use according to copyright law
DOI
10.1109/THERMINIC.2013.6675192
10.24406/publica-r-381732
Additional link
Full text
Language
English
Fraunhofer-Institut für Integrierte Schaltungen IIS  
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