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Electro-thermal co-design of chip-package-board systems

: Sohrmann, Christoph; Heinig, Andy; Dittrich, Michael; Jancke, Roland; Schneider, Peter

Preprint urn:nbn:de:0011-n-2706345 (801 KByte PDF)
MD5 Fingerprint: 6af45e019b37dac567a7e201905df686
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Created on: 12.8.2014

Institute of Electrical and Electronics Engineers -IEEE-:
19th International Workshop on Thermal Investigations of ICs and Systems, THERMINIC 2013 : Berlin, Germany, 25 - 27 September 2013
Piscataway, NJ: IEEE, 2013
ISBN: 978-1-4799-2271-0 (Print)
ISBN: 978-1-4799-2273-4 (online)
International Workshop on Thermal Investigations of ICs and Systems (THERMINIC) <19, 2013, Berlin>
Conference Paper, Electronic Publication
Fraunhofer IIS, Institutsteil Entwurfsautomatisierung (EAS) ()

We propose an innovative thermal modeling approach that takes into account different "levels-of-knowledge" as they become available during the design phases of microelectronic systems. There are many tools available for thermal simulations which are well-suited for high-precision modeling. However, their applicability severely diminishes if CAD models are not available or modeling time is limited. Especially for electro-thermal co-design, where several spins between modeling and simulation are required, modeling time quickly becomes prohibitively large. By a combination of different techniques our solution offers fast and intuitive modeling, continuous addition of detail, very short simulation times, and open interfaces. In this paper we present our thermal modeling approach based on constructive solid geometry (CSG). We discuss advantages and limits of this solution and demonstrate its performance on an example of industrially-relevant complexity.