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  • Publication
    Status of the demonstration of the critical technologies of the ATHENA telescope
    ( 2023)
    Ferreira, Ivo
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    Bavdaz, Marcos
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    Ayre, Mark
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    Wille, Eric
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    Brian Shortt
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    Fransen, Sebastiaan
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    Collon, Maximilien
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    Vacanti, Giuseppe
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    Barrière, Nicolas
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    Landgraf, Boris
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    Riekerink, Mark Olde
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    Haneveld, Jeroen
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    Start, Ronald
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    Baren, Coen van
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    Della Monica Ferreira, Desiree
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    Massahi, Sonny
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    Svendsen, Sara
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    Christensen, Finn
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    Krumrey, Michael
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    Skroblin, Dieter
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    Burwitz, Vadim
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    Pareschi, Giovanni
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    Tagliaferri, Gianpiero
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    Salmaso, Bianca
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    Basso, Stefano Maria Massimiliano
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    Moretti, Alberto
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    Spiga, Daniele
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    Valsecchi, Giuseppe
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    Vernani, Dervis
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    Lupton, Paul
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    Mundon, William
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    Gavin Phillips
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    Korhonen, Tapio
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    Sanchez Becerra, Alejandro
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    Heinis, Dominique
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    Colldelram, Carles
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    Tordi, Massimiliano
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    Willingale, Richard
    The ATHENA (Advanced Telescope for High ENergy Astrophysics) mission is the current 2nd ‘Large’ mission (L2) in the ESA Cosmic Vision programme currently. It is currently at Phase B1 but the mission concept will now enter a reformulation phase that will follow a design-to-cost approach. This paper describes the main technologies behind its reference X-ray telescope based on the modular Silicon Pore Optics (SPO) technology. The large X-ray mirror is the mission enabler being specifically developed for ATHENA, in a joint effort by industry, research institutions and ESA. All aspects of the optics are being addressed, from the mirror plates and their coatings to the mirror modules and their assembly into the ATHENA telescope, as well as the facilities required to build and test the flight optics, demonstrating performance, robustness, and programmatic compliance. An overview of the status of the design and demonstration of the telescope is given. The risks that have successfully been mitigated are made explicit and the remaining risks are identified. Additional presentation content can be accessed on the supplemental content page.
  • Publication
    Space Sampling Techniques Comparison for a Synthetic Low-Pass Filter Bayesian Neural Network
    ( 2023-12-08)
    Dávalos-Guzmán, Jorge
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    Chavez-Hurtado, Jose L.
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    Brito-Brito, Zabdiel
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    This paper presents a comparative analysis of three sampling techniques for generating space points to develop a Bayesian neural network (BNN) surrogate model of a synthetic second-order low-pass filter. The objective is to assess the effectiveness and efficiency of different sampling methods in the performance of the Bayesian surrogate model. The study draws inspiration from widely used sampling techniques such as uniform distribution, uniformly distributed random numbers, and Latin Hypercube Sampling (LHS). The results reveal that the BNN surrogate model achieves the best performance when using the LHS sampling method highlighting the impact of sampling techniques on the surrogate model's performance.
  • Publication
    Third Work Places als Treiber Kreativer Städte
    Seit einigen Jahren entwickeln sich insbesondere in der Büro- und Wissensarbeit eine Vielzahl unterschiedlicher Arbeitsorte unabhängig des Unternehmensstandortes. Sowohl Festangestellte als auch Selbstständige gehen ihrer Arbeitstätigkeit zunehmend an alternativen Arbeitsplätzen in Cafés, Bibliotheken, Transportmitteln oder Coworking Spaces nach. Sogenannte informelle und formelle Third Work Places prägen nicht nur die Arbeitswelt von morgen, sondern beeinflussen auch Stadtsysteme und ihre Infrastrukturen. Aufgrund der großen sozialen, wirtschaftlichen und räumlichen Relevanz von Third Work Places, stellt der vorliegende Beitrag den aktuellen Forschungsstand des Dissertationsvorhabens zur räumlichen Erscheinung, Nutzerstrukturen sowie Entwicklung von Third Work Places im Kontext kreativer Städte dar.
  • Publication
    LAT-UP: Exposing Layout-Level Analog Hardware Trojans Using Contactless Optical Probing
    ( 2023)
    Parvin, Sajjad
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    Goli, Mehran
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    Krachenfels, Thilo
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    Tajik, Shahin
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    Sill Torres, Frank
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    Drechsler, Rolf
    The insertion of a Hardware Trojan (HT) into a chip after the in-house layout design is outsourced to a chip manufacturer for fabrication is a major concern, especially for mission-critical applications. While several HT detection methods have been developed based on side-channel analysis and physical measurements to overcome this problem, there exist stealthy analog HTs, i.e., capacitive and dopant-level HTs, which have negligible or even zero overhead on the chip. Thus, these stealthy HTs cannot be detected using the aforementioned methods. In this work, we propose a novel analytical approach to detect these Layout-level Analog Trojans (LAT). Our proposed method uses an extension of Optical Probing (OP) for LAT detection, namely, the Laser Logic State Imaging (LLSI) technique. In principle, to detect LATs using LLSI, we only need the golden design and not a golden chip, which is not typically available. As we take advantage of LLSI to detect HTs, our approach is non-invasive, less costly, and scalable to larger designs. We report experimental results on a malicious RISC-V to demonstrate the effectiveness of our approach in detecting LATs.
  • Publication
    faulTPM: Exposing AMD fTPMs' Deepest Secrets
    ( 2023)
    Jacob, Hans Christian
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    Werling, Christian
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    Buhren, Robert
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    Trusted Platform Modules constitute an integral building block of modern security features. Moreover, as Windows 11 made a TPM 2.0 mandatory, they are subject to an ever-increasing academic challenge. While discrete TPMs - as found in higher-end systems - have been susceptible to attacks on their exposed communication interface, more common firmware TPMs (fTPMs) are immune to this attack vector as they do not communicate with the CPU via an exposed bus. In this paper, we analyze a new class of attacks against fTPMs: Attacking their Trusted Execution Environment can lead to a full TPM state compromise. We experimentally verify this attack by compromising the AMD Secure Processor, which constitutes the TEE for AMD's fTPMs. In contrast to previous dTPM sniffing attacks, this vulnerability exposes the complete internal TPM state of the fTPM. It allows us to extract any cryptographic material stored or sealed by the fTPM regardless of authentication mechanisms such as Platform Configuration Register validation or passphrases with anti-hammering protection. First, we demonstrate the impact of our findings by - to the best of our knowledge - enabling the first attack against Full Disk Encryption solutions backed by an fTPM. Furthermore, we lay out how any application relying solely on the security properties of the TPM - like Bitlocker's TPM- only protector - can be defeated by an attacker with 2-3 hours of physical access to the target device. Lastly, we analyze the impact of our attack on FDE solutions protected by a TPM and PIN strategy. While a naive implementation also leaves the disk completely unprotected, we find that BitLocker's FDE implementation withholds some protection depending on the complexity of the used PIN. Our results show that when an fTPM's internal state is compromised, a TPM and PIN strategy for FDE is less secure than TPM-less protection with a reasonable passphrase.