Interactive Design of Optimized Capacitance Arrays using Intelligent IP Layout Generators

Capacitance arrays are common building blocks in custom analog and mixed-signal integrated circuits (ICs). They are used for example in amplifiers, filters, and data converters to store precise amounts of electric charge. The usually strong accuracy requirements and related layout constraints often increase the effort required to find an optimal solution that considers both electrical behavior and layout properties. This paper demonstrates how our generator approach Intelligent IP can significantly reduce this effort. Its library of widely parametrizable building blocks, in particular the CapArray, is used to generate and evaluate circuit and layout variants that differ in device type, sizing, placement, and routing properties within seconds. This can be done either explicitly for individual variants or for an entire parameter space via a GUI or a script from within the usual design tool. We give an overview on the functionality for selected capacitance arrays, highlight the influence of selected parameters on layout area, aspect ratio, and parasitic-dependent accuracy, and finally show how this approach can be integrated in the design flow.