Simulation of process variations in FinFET transistor patterning

The impact of systematic process variations on the pattering for manufacturing of fin field effect transistors (FinFET) has been studied by means of physical-based lithography and topography simulation. To this end, a typical manufacturing sequence for a static random-access memory (SRAM) cell consisting of six transistors has been simulated. Within this sequence, self-aligned double pattering (SADP) is used to create the fin pattern and litho-etch-litho-etch (LELE) double pattering is applied to structure the gate electrodes. Based on the variations resulting from the manufacturing process, the frequency distributions for the fin width and for the gate length have been extracted. These distributions can be complemented by variations imposed by statistical effects to allow determination of the overall effect of systematic and statistical variations on the circuit behavior of the SRAM cell.