Design of a Time Gain Compensation Amplifier for an Ultrasound Analog Receiver Front End using 0.18 µm SOI Process

The work presents a time gain compensation amplifier as a part of ultrasound analog front-end circuit. The circuit compensates the attenuation which is experienced by the ultrasound echoes while traveling. The simulations have been done both for pre- and post-layout. The circuit is designed to interface 10 pF CMUT and to drive 5 pF capacitive load. The circuit provides 106 dB gain for the weakest echoes and linear in-dB 30 dB gain range with analog control. The noise at the maximum and minimum gain is 4.505 pA/pHz and 99.96 pA/pHz, respectively. The complete circuit consumes5.35mWand a total area of 0.03mm2 (210 m 141 m). The project is realized using0.18 m Silicon on Insulator (SOI) process technology from X-FAB. The simulation is done using Spectre in the Cadence Virtuoso with BS IM4v4.70 as the transistor model.