• English
  • Deutsch
  • Log In
    Password Login
    Research Outputs
    Fundings & Projects
    Researchers
    Institutes
    Statistics
Repository logo
Fraunhofer-Gesellschaft
  1. Home
  2. Fraunhofer-Gesellschaft
  3. Konferenzschrift
  4. Simulation of process variations in FinFET transistor patterning
 
  • Details
  • Full
Options
2016
Conference Paper
Title

Simulation of process variations in FinFET transistor patterning

Abstract
The impact of systematic process variations on the pattering for manufacturing of fin field effect transistors (FinFET) has been studied by means of physical-based lithography and topography simulation. To this end, a typical manufacturing sequence for a static random-access memory (SRAM) cell consisting of six transistors has been simulated. Within this sequence, self-aligned double pattering (SADP) is used to create the fin pattern and litho-etch-litho-etch (LELE) double pattering is applied to structure the gate electrodes. Based on the variations resulting from the manufacturing process, the frequency distributions for the fin width and for the gate length have been extracted. These distributions can be complemented by variations imposed by statistical effects to allow determination of the overall effect of systematic and statistical variations on the circuit behavior of the SRAM cell.
Author(s)
Baer, Eberhard  orcid-logo
Fraunhofer-Institut für Integrierte Systeme und Bauelementetechnologie IISB  
Burenkov, Alex  
Fraunhofer-Institut für Integrierte Systeme und Bauelementetechnologie IISB  
Evanschitzky, Peter  
Fraunhofer-Institut für Integrierte Systeme und Bauelementetechnologie IISB  
Lorenz, Juergen  
Fraunhofer-Institut für Integrierte Systeme und Bauelementetechnologie IISB  
Mainwork
International Conference on Simulation of Semiconductor Processes and Devices, SISPAD 2016  
Project(s)
SUPERTHEME  
Funder
European Commission EC  
Conference
International Conference on Simulation of Semiconductor Processes and Devices (SISPAD) 2016  
DOI
10.1109/SISPAD.2016.7605206
Language
English
Fraunhofer-Institut für Integrierte Systeme und Bauelementetechnologie IISB  
Keyword(s)
  • FinFET

  • SRAM cell

  • self-aligned double pattering

  • litho-etch-litho-etch double patterning

  • process simulation

  • systematic variations

  • Cookie settings
  • Imprint
  • Privacy policy
  • Api
  • Contact
© 2024