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Analysis of wafer process duration for ab initio calculation of capacity, throughput and bottleneck equipments in a wafer fab
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2004
Conference Paper
Title
Analysis of wafer process duration for ab initio calculation of capacity, throughput and bottleneck equipments in a wafer fab
Author(s)
Etzel, H.
Oertel, H.
Dudde, R.
Staudt, P.
Mainwork
Advancing the science and technology of semiconductor manufacturing excellence. ASMC 2004 Proceedings
Conference
Advanced Semiconductor Manufacturing Conference and Workshop (ASMC) 2004
DOI
10.1109/ASMC.2004.1309591
Language
English
Fraunhofer-Institut für Siliziumtechnologie ISIT
