Integration challenges for copper damascene electroplating

Copper electroplating has become the commonly used technology to manufacture interconnects in semiconductor products. The art of copper damascene electroplating is to provide a void-free fill for all design features, but to avoid high topography on top of those structures at the same time. The desired direction is superfill. The most widely published way to control this is to find the right electrolyte additive type and concentration for the features that have to be filled. However, there is a variety structures on a semiconductor chip and in a high-volume manufacturing there is a variety of products that may have different optimal fill conditions. In this paper, fill and topography control by current density modification and its implication to CMP will be shown.