Electroless plating on semiconductor wafers

In this work, we describe the concepts and results of electroless plating techniques on silicon wafers for two different applications: electroless bumping, and electroless plating for VLSI circuits. Flip chip technology requires the formation of bumps on semiconductor devices. Traditional bumping methods need expensive equipment for sputtering, photolithography and electroplating or evaporating. In contrast to the common techniques, the cost for a maskless wet-chemical bumping process is significantly lower. A chemical bumping technology developed and implemented at TUB/IZM is presented. The maskless process is based on electroless nickel deposition. Batches of 25 wafers of 150 mm diameter can be processed in a 30 l tank. The process time is determined by the nickel plating, which has a rate of 20 mu m/hour. The bump uniformity is better than 1 mu m for 20 mu m bumps on 100 mm wafers. For plating of very fine metal patterns such as contact holes and interconnections, we have developed a process based on electroless copper. The mechanical properties of copper deposits and the kinetics of electroless copper plating were analyzed for various types of baths. Selective copper plating introduces some new problems in general, such as compatibility with integrated circuit materials. There are also some particular problems that are associated with the technique, which are described here.