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PublicationCharacteristics of Li-ion micro batteries fully batch fabricated by micro-fluidic MEMS packaging( 2022)A cost-effective and reliable technology allowing extreme miniaturization of batteries into glass chips and electronic packages has been developed, employing a dispense-print process for battery electrodes and liquid electrolyte. Lithium-ion micro-batteries (active area 6 × 8 mm2, 0.15-0.3 mAh) with interdigitated electrodes were fabricated, tested and finally compared with the traditional battery architecture of stacked electrodes. Commercial graphite and lithium titanate anode as well as layered nickel cathode materials were used. All the processes for the micro-battery fabrication were established during this work; in particular the micro fluidic electrolyte filling process that allows simultaneous electrolyte supply to all cells on a planar substrate. Electrode mass reproducibility was sufficient for adequate electrode balancing. Current capability similar to the conventional face-to-face electrode configuration was achieved with interdigital electrodes that can be fabricated much easily on a substrate level. The cells were successfully cycled; several 100 cycles can be achieved. Additional results of life-time characteristics and electrochemical impedance spectroscopy are presented as well. These rechargeable micro-batteries can be used for future extremely miniaturized electronic products.
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PublicationCatastrophic Optical Damage in Semiconductor Lasers: Physics and New Results on InGaN High-Power Diode Lasers( 2022)Among the limitations known from semiconductor lasers, catastrophic optical damage (COD) is perhaps the most spectacular power-limiting mechanism. Here, absorption and temperature build up in a positive feedback loop that eventually leads to material destruction. Thus, this is truly an ultimate mechanism, and its continued suppression is a manifestation of progress in device design and manufacturing. After an overview of the current state of knowledge, new investigations of COD using artificially micrometer-sized starting points created within the active zone in the cavity of 450 nm GaN semiconductor lasers are reported on. Defect growth mechanisms and characteristics are studied during 800 ns current pulses. The defect growth follows the highest light intensity. Secondary defect patterns are studied: complete destruction of the active zone and generation of a point defect cloud at least ≈10 μm into the remaining surrounding material. Extremely large angles (>90°) of damage growth are traced back to the material properties and the aging scenario. The results are compared with former experiments with GaAs-based lasers.
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PublicationQuantum capacitance transient phenomena in high-k dielectric armchair graphene nanoribbon field-effect transistor model( 2021)Graphene Nanoribbons (GNRs) are an emerging candidate to challenge the place of current semiconductor-based technology. In this work, we extend a model for Armchair Graphene Nanoribbons Field-Effect Transistor (AGNRFET) to the high-k dielectrics realm and examine the influences of quantum capacitance on its transient phenomena. The model is coded with Verilog-A and evaluated through SPICE simulations. We have considered a comparison between the extended model with and without the influence of the quantum capacitance. Simulation results show a realistic scenario where influence of the quantum capacitance significantly impacts the transient behaviour in circuit design. This proves the proposed model to be a valuable aid for the circuit design of future graphene-based applications.
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PublicationA high temperature SOI-CMOS chipset focusing sensor electronics for operating temperatures up to 300 °C( 2021)Sensors are key elements for capturing environmental properties and are increasingly important in the industry for the intelligent control of industrial processes. While in many everyday objects highly integrated sensor systems are already state of the art, the situation in an industrial environment is clearly different. Frequently the use of sensor systems is impossible, because the extreme ambient conditions of industrial processes like high operating temperatures or strong mechanical load do not allow a reliable operation of sensitive electronic components. Fraunhofer is running the Lighthouse Project 'eHarsh' to overcome this hurdle. In the course of the project an integrated sensor readout electronic has been realized based on a set of three chips. A dedicated sensor frontend provides the analog sensor interface for resistive sensors typically arranged in a Wheatstone configuration. Furthermore, the chipset includes a 32-bit microcontroller for signal conditioning and sensor control. Finally, it comprises an interface chip including a bus transceiver and voltage regulators. The chipset has been realized in a high temperature 0.35 micron SOI-CMOS technology focusing operating temperatures up to 300 °C. The chipset is assembled on a multilayer ceramic LTCC-board using flip chip technology. The ceramic board consists of 4 layers with a total thickness of approx. 0.9 mm. The internal wiring is based on silver paste while external contacts were alternatively manufactured in silver (sintering/soldering) or in gold-alloys (wire bonding). As interconnection technology, silver sintering has been applied. It has already been shown that a significant increase in lifetime can be reached by using silver sintering for die attach applications. Using silver sintering for flip chip technology is a new and challenging approach. By adjusting the process parameter geared to the chipset design and the design of the ceramic board high quality flip chip interconnects can be generated.
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PatentAnordnung mit einem Substrat und zwei Bauelementen mit Lichtwellenleitern sowie Verfahren zur Herstellung( 2021)
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PublicationWashability of e-textiles: Current testing practices and the need for standardization( 2021)Washability is seen as one of the main obstacles that stands in the way of a wider market success of e-textile products. So far, there are no standardized methods for wash testing of e-textiles and no protocols to comparably assess the washability of tested products. Thus, different e-textiles that are deemed equally washable by their developers might present with very different ranges of reliability after repeated washing. This paper presents research into current test practices in the absence of e-textile-specific standards. Different testing methods are compared and evaluated and the need for standardized testing, giving e-textile developers the tools to comparably communicate and evaluate their products' washability, is emphasized.
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PublicationDesign for Circularity Guidelines for the EEE Sector( 2021)The increased diversity and complexity of plastics used in modern devices, such as electrical and electronic equipment (EEE), can have negative impacts on their recyclability. Today, the main economic driver for waste electrical and electronic equipment (WEEE) recycling stems from metal recovery. WEEE plastics recycling, on the other hand, still represents a major challenge. Strategies like design 'for', but also the much younger concept of design 'from' recycling play a key role in closing the material loops within a circular economy. While these strategies are usually analysed separately, this brief report harmonises them in comprehensive Design for Circularity guidelines, established in a multi-stakeholder collaboration with industry leaders from the entire WEEE value chain. The guidelines were developed at the product and part levels. They are divided in five categories: (1) avoidance of hazardous substances; (2) enabling easy access and removal of hazardous or polluting parts; (3) use of recyclable materials; (4) use of material combinations and connections allowing easy liberation; (5) use of recycled materials. These guidelines are the first harmonised set to be released for the EEE industry. They can readily serve decision-makers from different levels, including product designers and manufacturers as well as policymakers.
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PatentVerbindungsmethode für Leistungsmodule mit einer Zwischenkreisverschienung( 2021)System umfassend ein Leistungsmodul umfassend einen Halbleiter und eine erste Verbindungsstelle und eine zweite Verbindungsstelle, die mit dem Halbleiter elektrisch leitend verbunden ist sowie eine Zwischenkreisverschienung umfassend zumindest zwei Schienen, wobei eine erste der zwei Schienen zumindest ein Kontaktelement aufweist, und wobei das zumindest eine Kontaktelement mit der ersten Verbindungsstelle eine elektrisch leitende Kaltverschweißverbindung formt.
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PublicationA New Filter Concept for High Pulse-Frequency 3-Phase AFE Motor Drives( 2021)The size of back-to-back converters with active front end is significantly determined by the size of the passive filter components. This paper presents a new complete EMC filter concept for this type of converter system that is effective on the input and the output. This involves filtering the main common mode interferences from the grid and motor sides with a single CM choke. Since only the difference of the generated common mode voltage-time areas of both converters is absorbed by this component, the size of the required filter can be greatly reduced compared to conventional filter concepts. The concept is validated on a grid feeding inverter that can be connected to the public distribution network with an output power of 63 kW. The size reduction is demonstrated by means of a design example on a system with the same power and electrical requirements. It is elaborated why, applying the new filter concept, the impedance of the DC link potentials to ground and other electrical potentials should be as high as possible and therefore associated parasitic capacitances should be minimized. From this requirement, rules for the design of the power modules of PFC and motor converters for the application of this filter concept are derived.
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PublicationCo-Package Technology Platform for Low-Power and Low-Cost Data Centers( 2021)We report recent advances in photonic-electronic integration developed in the European research project L3MATRIX. The aim of the project was to demonstrate the basic building blocks of a co-packaged optical system. Two-dimensional silicon photonics arrays with 64 modulators were fabricated. Novel modulation schemes based on slow light modulation were developed to assist in achieving an efficient performance of the module. Integration of DFB laser sources within each cell in the matrix was demonstrated as well using wafer bonding between the InP and SOI wafers. Improved semiconductor quantum dot MBE growth, characterization and gain stack designs were developed. Packaging of these 2D photonic arrays in a chiplet configuration was demonstrated using a vertical integration approach in which the optical interconnect matrix was flip-chip assembled on top of a CMOS mimic chip with 2D vertical fiber coupling. The optical chiplet was further assembled on a substrate to facilitate integration with the multi-chip module of the co-packaged system with a switch surrounded by several such optical chiplets. We summarize the features of the L3MATRIX co-package technology platform and its holistic toolbox of technologies to address the next generation of computing challenges.
