Fraunhofer-Institut für Zuverlässigkeit und Mikrointegration IZM

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  • Publication
    Electroless plating on semiconductor wafers
    ( 1999)
    Aschenbrenner, R.
    ;
    Ostmann, A.
    ;
    Reischl, H.
    In this work, we describe the concepts and results of electroless plating techniques on silicon wafers for two different applications: electroless bumping, and electroless plating for VLSI circuits. Flip chip technology requires the formation of bumps on semiconductor devices. Traditional bumping methods need expensive equipment for sputtering, photolithography and electroplating or evaporating. In contrast to the common techniques, the cost for a maskless wet-chemical bumping process is significantly lower. A chemical bumping technology developed and implemented at TUB/IZM is presented. The maskless process is based on electroless nickel deposition. Batches of 25 wafers of 150 mm diameter can be processed in a 30 l tank. The process time is determined by the nickel plating, which has a rate of 20 mu m/hour. The bump uniformity is better than 1 mu m for 20 mu m bumps on 100 mm wafers. For plating of very fine metal patterns such as contact holes and interconnections, we have developed a process based on electroless copper. The mechanical properties of copper deposits and the kinetics of electroless copper plating were analyzed for various types of baths. Selective copper plating introduces some new problems in general, such as compatibility with integrated circuit materials. There are also some particular problems that are associated with the technique, which are described here.
  • Publication
    Reliability investigations of flip chip interconnects in FCOB and FCOG applications by FEA
    ( 1998)
    Schubert, A.
    ;
    Dudek, R.
    ;
    Döring, R.
    ;
    Michel, B.
    One major concern over thermally induced mechanical stress is that it causes reliability problems in electronic device packaging and interconnects. IC packaging has accelerated development of flip chip structures as used in flip chip on board (FCOB) or flip chip on glass (FCOG) technology. Much testing is usually required to meet the reliability needs of an assembly or to optimize its design. Finite element analysis (FEA) is used to understand the reasons for failure and the critical parameters which may be varied; however, use of FEA generates difficulties concerning the geometrical description and constitutive modeling of the materials used. Solder joints, the most widely used FCOB interconnects, have relatively low structural compliance due to the large CTE mismatch between die and organic substrate. This causes high thermally induced creep strain on interconnects during temperature cycling and leads to early failure. Flip chip reliability can be enhanced by applying an epoxy-based underfill between chip and substrate. However, over ranges of design, process and material parameters, different failure modes are observed with significant dependence on material properties and geometry. Nonlinear FEA of flip chip structures is carried out to study the reliability impact of selected design and material parameters. Two fundamental issues are addressed: optimized manufacturing process-induced defects and underfill material thermo-mechanical properties. Anisotropic conductive films (ACF) are widely used for FCOG packaging. Nonlinear FEA simulations are conducted to investigate stress development and relaxation in ACF joints.
  • Publication
    Low cost bumping by stencil printing. Process qualification for 200 mu m pitch
    ( 1998)
    Klöser, J.
    ;
    Heinricht, K.
    ;
    Jung, E.
    ;
    Lauter, L.
    ;
    Ostmann, A.
    ;
    Aschenbrenner, R.
    ;
    Reichl, H.
    A key issue for the introduction of flip chip technology for automotive, telecommunication and consumer applications is the implementation of low cost bumping processes, since the established methods need expensive equipment for metal sputtering and photolithography. At present, there are several methods for creating bumps on the die. One new method that has the potential to be much less expensive than current technologies is stencil printing. In this paper, the stencil printing method for wafer solder bumping is described using electroless nickel as a layer between the IC bond pad and the solder. Stencil printing for SMT and fine pitch BGA structures is established as a low cost standard process. Using the same equipment with modified printing parameters and materials, a low cost wafer bumping process has been transferred to serial production. This paper presents the results of ultra fine pitch stencil printing of solder paste on wafers (down to 200 mu m and 150 mu m pitch) discussing quality and yield. A software tool for stencil layout design was developed and predicted bump heights are compared to experimental results. In the first part of the paper, the process flow of this economical bumping method for flip chip technology is described in detail. The key aspects of solder paste printing with optimized aperture size and shapes are outlined and the printing results are presented. In the second part of the paper, a comparison of measured standard deviations of bump heights and the quality demands for ultra fine pitch flip chip assembly are also shown.
  • Publication
    Characterization of adhesive materials for high circuit density applications
    ( 1998)
    Aschenbrenner, R.
    ;
    Mießner, R.
    ;
    Becker, K.-F.
    ;
    Reichl, H.
    This report presents the results of the evaluation of isotropic and anisotropic conductive adhesives for flip chip and chip size package applications. Samples consist of bumped testchips mounted on fine pitch rigid and flexible substrates. The finest pitch of the rigid glass substrates is 70 mu m and for the flexible substrates 100 mu m. Promising candidate for adhesive joining technique are the isotropic conductive adhesives. These adhesives are isotropic, which means that they conduct electricity equally in all directions. To use such adhesives in flip chip applications, the material has to be applied precisely onto the points to be connected, and is not allowed to flow and short circuit between circuit lines. The anisotropicaliy conductive adhesive materials are prepared by dispersing electrically conductive particles in an adhesive matrix at a concentration that is high enough to assure reliable conductivity between the substrate and the IC electrodes. The reliability evaluation was performed with special regard to the degradation and to the interface reactions between polymers and metal surfaces in adhesive contacts. The electrical and mechanical performance of the adhesive bonds were studied by evaluating initial contact resistance and mechanical adhesion as a function of temperature and humidity. A detailed thermo-mechanical analysis was used to determine the optimal cure schedule and to characterize the materials according to their physical properties. This kind of analysis method has also been used to optimize the curing profile, i.e. to shorten the curing time.
  • Publication
    Implementation of flip chip technology into volume manufacturing demonstration of processes
    ( 1998)
    Jung, E.
    ;
    Heinricht, K.
    ;
    Kutzner, K.
    ;
    Klöser, J.
    ;
    Aschenbrenner, R.
    ;
    Reichl, H.
    ;
    Brommelhaus, A.
    Until now, use of flip chip technology has not been widespread in volume manufacturing, although it provides a number of significant advantages over standard surface mount devices. In particular, the cost aspect of using flip chip technology in a large scale manufacturing environment is expected to overcome the remaining issues. In order to illustrate the equipment and processes involved for incorporation of flip chip attachment into a production process, a demonstration center was established at FhG-IZM. Critical process steps were identified and addressed. This article gives a detailed insight into the actual implementation of a flip chip process into a SMD compatible production line, highlighting aspects of bump provision, cleaning, chip placement and underfilling. Bumping covers low cost processes such as electroless nickel as under-bump metallization (UBM) and stencil printed solder deposits using advanced printing technology. The necessity of cleaning and the key aspects for achievement of high reliability with industrial applied processes is highlighted. Required features of the placement machine and related critical issues are presented. Underfill application is also covered, focussing on important aspects for process optimization.
  • Publication
    Thermo-mechanical reliability of flip chip structures used in DCA and CSP
    ( 1998)
    Schubert, A.
    ;
    Dudek, R.
    ;
    Vogel, D.
    ;
    Michel, B.
    ;
    Reichl, H.
    The continuing demand towards high-density and low profile integrated circuit packaging has accelerated the development of flip chip structures as used in direct chip attach (DCA) technology and chip size packages (CSP). The advantages in density, cost and electrical performance are obvious. Solder joints, the most widely used flip chip interconnects, have a relatively low structural compliance due to the large thermal expansion mismatch between silicon die and the organic substrate. This causes high thermally induced creep strain on the interconnects during temperature cycling and leads to early failure of the solder connections. The reliability of flip chip structures can be enhanced by applying an epoxy-based underfill between the chip and the substrate, encapsulating the solder joints. However, over ranges of design, process, and material parameters, different failure modes are observed with significant dependence on material properties and geometry. Nonlinear finite element analysis for flip chip structures is carried out to investigate the reliability impact due to a number of selected design and material parameters. Especially two fundamental issues are addressed, namely, the optimization of thermomechanical properties of underfill materials and manufacturing process-induced defects.
  • Publication
    Correlation of thermo-mechanical properties of adhesives with reliability of FC interconnections
    ( 1998)
    Mießner, R.
    ;
    Aschenbrenner, R.
    ;
    Reichl, H.
    This paper presents an evaluation of isotropic and anisotropic conductive adhesives for flip chip applications. Samples consist of bumped test chips mounted on fine pitch rigid and flexible substrates. The finest pitches are 150 mu m for rigid FR4 substrates and 100 mu m for flex substrates. Isotropic conductive adhesives are promising candidates for adhesive joining. As they conduct electricity equally in all directions, the material must be applied precisely to the points to be connected, and not allowed to flow and short circuit between circuit lines. Anisotropic conductive adhesive materials are prepared by dispersing electrically conductive particles in an adhesive matrix. The concentration assures reliable conductivity between substrate and IC electrodes but insulation between adjacent bumps. Several adhesives, both commercial and experimental products, were investigated. A detailed thermo-mechanical analysis was used to characterize the materials according to their physical properties. This analysis method was also used to optimize the curing profile, i.e. to shorten curing time. The reliability evaluation was performed with special regard to the degradation and to interface reactions between polymers and metal surfaces in adhesive contacts. The electrical and mechanical performance of the adhesive bonds were studied by evaluating initial contact resistance and mechanical adhesion as a function of temperature and humidity. Reliability test data was correlated with the thermo-mechanical properties. We thus derived simple criteria for adhesive selection for flip chip applications.
  • Publication
    Thermo-mechanical analysis of microelectronics components and chipcards
    ( 1998)
    Michel, B.
    ;
    Vogel, D.
    This paper presents the results of a series of experiments and combined numerical simulations for advanced electronic packaging structures. With growing miniaturization the "local" material properties and local temperature gradients exert a greater influence on the reliability of microcomponents and microsystems than in any macroscopic component. The authors apply such experimental techniques as acousto-microscopy, laser scanning microscopy, thermography, and the microDAC method to characterize the material behaviour of microelectronic packaging components. The experiments have been combined directly with FE simulations. This finally leads to an improved reliability assessment of the microcomponents (e.g. chip cards, airbag sensor components). Special attention is also given to the experimental analysis of thermal fatigue behaviour of solder bumps in microsolder interconnects of flip chip assemblies and chip size packages. These problems are very important for applications in automotive electronics and telecommunication as well.
  • Publication
    Alternative solders for flip chip applications in the automotive environment
    ( 1998)
    Jung, E.
    ;
    Heinricht, K.
    ;
    Klöser, J.
    ;
    Aschenbrenner, R.
    ;
    Reichl, H.
    In addition to Pb toxicity, there are other problems with SnPb solders. In automotive applications, where solder joints are subjected to thermal cycles, severe vibrations, sustained temperatures up to 150 degrees C and peak temperatures of 180 degrees C, the critical failure mode of eutectic SnPb solder in assemblies is bump fatigue. For flip chip technology, induced thermal stresses and strains in solder joints are very hazardous. This paper presents a flip chip process based on electroless Ni/Au bumping and stencil printing of solder paste on wafers. Chemical nickel plating combined with solder printing is a very flexible and cost effective bumping method. The basic process steps and key aspects of this technology are described in detail. Experimental results for an ultra fine pitch printing technique on wafers are shown, and reflowed solder bumps are characterized for uniformity and strength. In comparison to eutectic SnPb, SnBiCu, SnAg, SnCu, and AuSn solder alloys are selected and investigated. The alloys are compared for flip chip technology applicability, microstructure and phase compositions are presented. Microstructure coarsening and phase growth after thermal aging are also investigated. In order to investigate substrate material CTE effects on reliability, flip chip assembly was performed on low temperature cofired ceramic (LTCC) and FR-4 substrates. The flip chip joint quality was investigated by metallurgical cross sections and electrical and mechanical measurements. Finally, the reliability results of these joints after thermal cycling with and without underfill on both types of substrate materials are presented.
  • Publication
    Quality and yield of ultra fine pitch stencil printing for flip chip assembly
    ( 1998)
    Heinricht, K.
    ;
    Klöser, J.
    ;
    Lauter, L.
    ;
    Ostmann, A.
    ;
    Reichl, H.
    ;
    Wolter, A.
    Stencil printing for SMT and fine pitch BGA structures is established as a low cost standard process. Using the same equipment with modified printing parameters and materials, a low cost bumping process has been transferred to serial production. This paper presents the results of ultra fine pitch stencil printing of solder paste on wafers (down to 200 mu m and 150 mu m pitch) with regard to quality and yield. A software tool for design of the stencil layout was developed and the predicted bump heights were compared to the experimental results. In the first part of the paper, a low cost bumping method for flip chip technology is described in detail. This technology is based on chemical Ni/Au deposition on wafers. For solder bumping on wafers, the key aspects of solder paste printing with optimized printable apertures are described and the printing results are presented. The second part of this paper is a comparison of measured standard deviations of bump heights and the quality demands for ultra fine pitch flip chip assembly.