Fraunhofer-Institut für Zuverlässigkeit und Mikrointegration IZM

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  • Publication
    3D integration of image sensor SiP using TSV silicon interposer
    ( 2009)
    Wolf, M.J.
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    Zoschke, K.
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    Klumpp, A.
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    Wieland, R.
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    Klein, M.
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    Nebrich, L.
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    Heinig, A.
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    Limansyah, I.
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    Weber, W.
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    Ehrmann, O.
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    Reichl, H.
    3D system integration is a fast growing field that encompasses different types of technologies. The technology chosen for a specific application will be selected according to the required electrical performance of the systems, the footprint, cost and time to market. Other important factors are the boundary conditions given for the specific components e.g. die size, integration compatibility, component availability (wafer vs. bare die) and testability. The paper discusses a specific 3D image sensor system for automotive applications. The system is based on wafer level technology using silicon interposer with through silicon vias (TSV's), a flip chip assembled sensor element and a microcontroller. The specific system concept, the technical solution and results are discussed.
  • Publication
    Electroless plating on semiconductor wafers
    ( 1999)
    Aschenbrenner, R.
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    Ostmann, A.
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    Reischl, H.
    In this work, we describe the concepts and results of electroless plating techniques on silicon wafers for two different applications: electroless bumping, and electroless plating for VLSI circuits. Flip chip technology requires the formation of bumps on semiconductor devices. Traditional bumping methods need expensive equipment for sputtering, photolithography and electroplating or evaporating. In contrast to the common techniques, the cost for a maskless wet-chemical bumping process is significantly lower. A chemical bumping technology developed and implemented at TUB/IZM is presented. The maskless process is based on electroless nickel deposition. Batches of 25 wafers of 150 mm diameter can be processed in a 30 l tank. The process time is determined by the nickel plating, which has a rate of 20 mu m/hour. The bump uniformity is better than 1 mu m for 20 mu m bumps on 100 mm wafers. For plating of very fine metal patterns such as contact holes and interconnections, we have developed a process based on electroless copper. The mechanical properties of copper deposits and the kinetics of electroless copper plating were analyzed for various types of baths. Selective copper plating introduces some new problems in general, such as compatibility with integrated circuit materials. There are also some particular problems that are associated with the technique, which are described here.
  • Publication
    Integration of flip chip assembly in the SMT process: manufacturing and productivity issues
    ( 1998)
    Jung, E.
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    Klöser, J.
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    Heinricht, K.
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    Lauter, L.
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    Aschenbrenner, R.
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    Reichl, H.
    Increasing interest in cost effective flip chip technologies leads to the development of various flexible methods for the deposition of solders and adhesives for use on chip or substrate. In this paper, the elements and basic process steps required for the development of a cost effective and flexible flip chip technology are described in detail. The deposition methods are focused on processes for stencil printing of solder paste on wafers and substrates. To achieve reproducible and homogeneous solder deposits, the process techniques for fine pitch printing require an improvement of the physical properties of the solder paste, of the stencil materials and stencil processing technologies, and of the printing equipment. Using solder pastes with very small particle sizes, a N2 atmosphere and a well controlled reflow furnace temperature profile is required. Apart from the technological aspects, the key point for the introduction of flip chip technology in a wide field of applications is the production equipment. The Fraunhofer Institute together with several industrial partners has set up a demonstration center for the assembly of flip chips (FC) and chip size packages (CSP). It is important to note that flip chip and CSPs can be used in conjunction with standard surface mount technology (SMT) devices. The development of these processes was performed by simultaneous engineering. In this paper, the experimental works are focused on the low cost bumping and assembly of flip chips and CSPs together with SMDs on different substrates.
  • Publication
    Correlation of thermo-mechanical properties of adhesives with reliability of FC interconnections
    ( 1998)
    Mießner, R.
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    Aschenbrenner, R.
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    Reichl, H.
    This paper presents an evaluation of isotropic and anisotropic conductive adhesives for flip chip applications. Samples consist of bumped test chips mounted on fine pitch rigid and flexible substrates. The finest pitches are 150 mu m for rigid FR4 substrates and 100 mu m for flex substrates. Isotropic conductive adhesives are promising candidates for adhesive joining. As they conduct electricity equally in all directions, the material must be applied precisely to the points to be connected, and not allowed to flow and short circuit between circuit lines. Anisotropic conductive adhesive materials are prepared by dispersing electrically conductive particles in an adhesive matrix. The concentration assures reliable conductivity between substrate and IC electrodes but insulation between adjacent bumps. Several adhesives, both commercial and experimental products, were investigated. A detailed thermo-mechanical analysis was used to characterize the materials according to their physical properties. This analysis method was also used to optimize the curing profile, i.e. to shorten curing time. The reliability evaluation was performed with special regard to the degradation and to interface reactions between polymers and metal surfaces in adhesive contacts. The electrical and mechanical performance of the adhesive bonds were studied by evaluating initial contact resistance and mechanical adhesion as a function of temperature and humidity. Reliability test data was correlated with the thermo-mechanical properties. We thus derived simple criteria for adhesive selection for flip chip applications.
  • Publication
    Experience with a fully automatic flip-chip assembly line integrating SMT
    ( 1998)
    Klöser, J.
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    Kutzner, K.
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    Jung, E.
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    Heinricht, K.
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    Lauter, L.
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    Töpper, M.
    The Fraunhofer Institute (FhG/IZM-Berlin) together with several industrial partners has set up a demonstration center for the assembly of flip chips (FC) and chip size packages (CSP). It consists of a complete production line, and additional equipment for quality control and process development. The central interest is the implementation of cost effective, high reliability and environmentally friendly processes. To achieve these goals, upscaling existing flip chip technologies from laboratory examples to industrial production is necessary. At the same time, the technologies must be optimized to guarantee a high quality standard and good yield in high volume production. In order to demonstrate the high performance of these cost effective flip chip technologies, the process flows of different flip chip assembly techniques using solder are compared and described in detail. It is important to note that flip chips and CSPs can be used in conjunction with standard surface mount technology (SMT) devices. The development of these processes was performed by simultaneous engineering. Finally, the yield and costs are estimated and the reliability results of a selected flip chip process are presented.
  • Publication
    Reliability investigations for flip chip on flex using different solder materials
    ( 1998)
    Kallmayer, C.
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    Oppermann, H.
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    Anhöck, S.
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    Azadeh, R.
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    Aschenbrenner, R.
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    Reichl, H.
    Flip chip assembly on flexible organic substrates is facing increasing interest. In consumer products such as mobile phones or pagers, the assembly of the drivers of the LCD displays can be realized this way. Also there is a growing demand for Chip Size Packages (CSP). As a low cost version, CSPs based on flexible interposers have been developed. Especially for this application the reliability of the assemblies is important. Little is known about the aging behavior of these packages with different solder materials such as Pb-Sn and Au-Sn on standard tape metallizations as Cu-Au or Cu-Ni-Au. The impact of the bumping technology on the reliability is also a subject. Electroplated bumps are studied in comparison with meniscus bumps. Based on electroless Ni bumping, this cost effective technology is especially suited for flip chip on flex as the solder volume deposited is very small. In order to make useful predictions about the reliability of a metallurgical system it is necessary to understand the basic reactions involved. The scope of the investigations presented in this paper is to gain the data on interdiffusion in these systems, on the formation and growth of intermetallic phases. The impact of the presence of intermetallics and voids on the mechanical reliability is determined. The test program includes annealing of the flip chip assemblies at different temperatures and thermal cycling. Electrical measurements (Daisy chain) and shear tests are performed to determine the electrical and mechanical degradation of the solder joints.
  • Publication
    Alternative solders for flip chip applications in the automotive environment
    ( 1998)
    Jung, E.
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    Heinricht, K.
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    Klöser, J.
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    Aschenbrenner, R.
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    Reichl, H.
    In addition to Pb toxicity, there are other problems with SnPb solders. In automotive applications, where solder joints are subjected to thermal cycles, severe vibrations, sustained temperatures up to 150 degrees C and peak temperatures of 180 degrees C, the critical failure mode of eutectic SnPb solder in assemblies is bump fatigue. For flip chip technology, induced thermal stresses and strains in solder joints are very hazardous. This paper presents a flip chip process based on electroless Ni/Au bumping and stencil printing of solder paste on wafers. Chemical nickel plating combined with solder printing is a very flexible and cost effective bumping method. The basic process steps and key aspects of this technology are described in detail. Experimental results for an ultra fine pitch printing technique on wafers are shown, and reflowed solder bumps are characterized for uniformity and strength. In comparison to eutectic SnPb, SnBiCu, SnAg, SnCu, and AuSn solder alloys are selected and investigated. The alloys are compared for flip chip technology applicability, microstructure and phase compositions are presented. Microstructure coarsening and phase growth after thermal aging are also investigated. In order to investigate substrate material CTE effects on reliability, flip chip assembly was performed on low temperature cofired ceramic (LTCC) and FR-4 substrates. The flip chip joint quality was investigated by metallurgical cross sections and electrical and mechanical measurements. Finally, the reliability results of these joints after thermal cycling with and without underfill on both types of substrate materials are presented.
  • Publication
    Quality and yield of ultra fine pitch stencil printing for flip chip assembly
    ( 1998)
    Heinricht, K.
    ;
    Klöser, J.
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    Lauter, L.
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    Ostmann, A.
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    Reichl, H.
    ;
    Wolter, A.
    Stencil printing for SMT and fine pitch BGA structures is established as a low cost standard process. Using the same equipment with modified printing parameters and materials, a low cost bumping process has been transferred to serial production. This paper presents the results of ultra fine pitch stencil printing of solder paste on wafers (down to 200 mu m and 150 mu m pitch) with regard to quality and yield. A software tool for design of the stencil layout was developed and the predicted bump heights were compared to the experimental results. In the first part of the paper, a low cost bumping method for flip chip technology is described in detail. This technology is based on chemical Ni/Au deposition on wafers. For solder bumping on wafers, the key aspects of solder paste printing with optimized printable apertures are described and the printing results are presented. The second part of this paper is a comparison of measured standard deviations of bump heights and the quality demands for ultra fine pitch flip chip assembly.
  • Publication
    Low cost bumping by stencil printing. Process qualification for 200 mu m pitch
    ( 1998)
    Klöser, J.
    ;
    Heinricht, K.
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    Jung, E.
    ;
    Lauter, L.
    ;
    Ostmann, A.
    ;
    Aschenbrenner, R.
    ;
    Reichl, H.
    A key issue for the introduction of flip chip technology for automotive, telecommunication and consumer applications is the implementation of low cost bumping processes, since the established methods need expensive equipment for metal sputtering and photolithography. At present, there are several methods for creating bumps on the die. One new method that has the potential to be much less expensive than current technologies is stencil printing. In this paper, the stencil printing method for wafer solder bumping is described using electroless nickel as a layer between the IC bond pad and the solder. Stencil printing for SMT and fine pitch BGA structures is established as a low cost standard process. Using the same equipment with modified printing parameters and materials, a low cost wafer bumping process has been transferred to serial production. This paper presents the results of ultra fine pitch stencil printing of solder paste on wafers (down to 200 mu m and 150 mu m pitch) discussing quality and yield. A software tool for stencil layout design was developed and predicted bump heights are compared to experimental results. In the first part of the paper, the process flow of this economical bumping method for flip chip technology is described in detail. The key aspects of solder paste printing with optimized aperture size and shapes are outlined and the printing results are presented. In the second part of the paper, a comparison of measured standard deviations of bump heights and the quality demands for ultra fine pitch flip chip assembly are also shown.
  • Publication
    Thermo-mechanical reliability of flip chip structures used in DCA and CSP
    ( 1998)
    Schubert, A.
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    Dudek, R.
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    Vogel, D.
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    Michel, B.
    ;
    Reichl, H.
    The continuing demand towards high-density and low profile integrated circuit packaging has accelerated the development of flip chip structures as used in direct chip attach (DCA) technology and chip size packages (CSP). The advantages in density, cost and electrical performance are obvious. Solder joints, the most widely used flip chip interconnects, have a relatively low structural compliance due to the large thermal expansion mismatch between silicon die and the organic substrate. This causes high thermally induced creep strain on the interconnects during temperature cycling and leads to early failure of the solder connections. The reliability of flip chip structures can be enhanced by applying an epoxy-based underfill between the chip and the substrate, encapsulating the solder joints. However, over ranges of design, process, and material parameters, different failure modes are observed with significant dependence on material properties and geometry. Nonlinear finite element analysis for flip chip structures is carried out to investigate the reliability impact due to a number of selected design and material parameters. Especially two fundamental issues are addressed, namely, the optimization of thermomechanical properties of underfill materials and manufacturing process-induced defects.