Fraunhofer-Institut für Zuverlässigkeit und Mikrointegration IZM

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  • Publication
    Towards cube-sized compute nodes: Advanced packaging concepts enabling extreme 3D integration
    ( 2018)
    Brunschwiler, T.
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    Schlottig, G.
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    Sridhar, A.
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    Bezerra, P.
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    Ruch, P.
    ;
    Ebejer, N.
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    Oppermann, H.
    ;
    Kleff, J.
    ;
    Steller, W.
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    Jatlaoui, M.
    ;
    Voiron, F.
    ;
    Pavlovic, Z.
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    McCloskey, P.
    ;
    Bremner, D.
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    Parida, P.
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    Krismer, F.
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    Kolar, J.
    ;
    Michel, B.
    Novel heat removal and power delivery topologies are required to enable `extreme 3D integration' with cube-sized compute nodes. Therefore, a technology roadmap is presented supporting memory-on-logic and logic-on-logic in the medium and long-term, by (i) dual-side cooling and integrated voltage regulators, and (ii) interlayer cooling and electrochemical power delivery.
  • Publication
    On the crack and delamination risk optimization of a Si-interposer for LED packaging
    ( 2013)
    Auersperg, J.
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    Dudek, R.
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    Jordan, R.
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    Bochow-Neß, O.
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    Rzepka, S.
    ;
    Michel, B.
    3D-integration becomes more and more an important issue for advanced LED packaging solutions as it is a great challenge for the thermo-mechanical reliability to remove heat from LEDs to the environment by heat spreading or specialized cooling technologies. Thermal copper-TSVs provide an elegant solution to effectively transfer heat from LED to the heat spreading structures on the backside of a substrate. But, the use of copper-TSVs generates also novel challenges for reliability as well as also for reliability analysis and prediction, i.e. to manage multiple failure modes acting combined - interface delamination, cracking and fatigue, in particular. In this case, the thermal expansion mismatch between copper and silicon yields to risky stress situations. Therefore, the authors performed extensive simulative work to overcome cracking and delamination risks in the vicinity of thermal copper-TSVs by means of fracture mechanics approaches. Especially, an interaction integral approach is utilized within a simulative DoE and X-FEM is used to help clarifying crack propagation paths in silicon. The DoE-based response surface methodology provided a good insight into the role of model parameters for further optimizations of the intended thermal TSV-approaches in LED packaging applications.
  • Publication
    Advanced mixed-mode bending test: A rapid, inexpensive and accurate method for fracture-mechanical interface characterisation
    ( 2012)
    Wunderle, B.
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    Schulz, M.
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    Keller, J.
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    Maus, I.
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    Pape, H.
    ;
    Michel, B.
    This paper presents a comprehensive method for obtaining urgently required critical interface delamination data of material pairings used in electronic packaging. The objective is to thereby enable rapid, inexpensive and accurate lifetime prediction for that failure mode. A new testing method is presented which allows maximummode-angle range and enhanced throughput testing under multiple loading conditions, the coverage of which is usually a rather lengthy and resource-demanding procedure. The approach is specimen-centred in the sense that the accent is put on test-specimens which are easily manufacturable industrially, rather than having to adapt them to a special testing machine. The concept is also scalable, i.e. it has potential to work also for smaller samples cut fromreal devices. We show the first version of a newly developed test-stand and discuss the obtained results for copper-molding compound interfaces in the light of the current state of the art used for de lamination testing in electronic packaging.
  • Publication
    Advanced mixed-mode bending test: A rapid, inexpensive and accurate method for fracture-mechanical interface characterisation
    ( 2012)
    Wunderle, B.
    ;
    Schulz, M.
    ;
    Keller, J.
    ;
    May, D.
    ;
    Maus, I.
    ;
    Pape, H.
    ;
    Michel, B.
    This paper presents a comprehensive method for obtaining urgently required critical interface delamination data of material pairings used in electronic packaging. The objective is to thereby enable rapid, inexpensive and accurate lifetime prediction for that failure mode. A new testing method is presented which allows maximum mode-angle range and enhanced throughput testing under multiple loading conditions, the coverage of which is usually a rather lengthy and resource-demanding procedure. The approach is specimen-centred in the sense that the accent is put on test-specimens which are easily manufacturable industrially, rather than having to adapt them to a special testing machine. The concept is also scalable, i.e. it has potential to work also for smaller samples cut from real devices. We show the first version of a newly developed test-stand and discuss the obtained results for copper-molding compound interfaces in the light of the current state of the art used for delamination testing in electronic packaging.
  • Publication
    Reliability analysis of low temperature low pressure Ag-sinter die attach
    ( 2011)
    Mroßko, R.
    ;
    Oppermann, H.
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    Wunderle, B.
    ;
    Michel, B.
    The amount of heat to be dissipated from power electronics and microprocessors increases more and more. Therefore new interface materials with high electrical and thermal conductivity have to be considered. Silver is one of a few materials which can fulfil these demands. New low temperature, low pressure Ag-Sinter technologies allow it to use Silver as die attach material instead of solder or glue. Even though silver has excellent thermal and electrical properties, thermo-mechanical reliability aspects have to be considered. In this paper the thermo-mechanical reliability of chip-on-board (COB) assemblies for power applications are studied by experiment and simulation. Thereby the main focus is set on the characterization methods and low cycle fatigue failure behaviour of the die-attach material under thermal cycling conditions. Part of the work has been accomplished within the running EU Project "Nanopack".
  • Publication
    Local stress measurement on metal lines and dielectrics of BEoL pattern by stress relief technique
    ( 2011)
    Vogel, D.
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    Rzepka, S.
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    Michel, B.
    ;
    Gollhardt, A.
    The paper presents a new measurement method for residual stresses introduced by manufacturing in BEoL structures. Material removal by FIB ion milling is used to release elastically frozen stresses. Normal stress components are calculated from local stress relaxation nearby milled trenches. A validation of the new technique is accomplished by additional bow measurements on defined layers on substrate. Spatially resolved determination of stress values in metal lines and the dielectrics in between demonstrates the capability of the tool for future applications.
  • Publication
    Angle-of-attack investigation of pin-fin arrays in nonuniform heat-removal cavities for interlayer cooled chip stacks
    ( 2011)
    Brunschwiler, T.
    ;
    Paredes, S.
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    Drechsler, U.
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    Michel, B.
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    Wunderle, B.
    ;
    Reichl, H.
    Interlayer cooling removes the heat dissipated by vertically stacked chips in multiple integrated fluid cavities. Its performance scales with the number of dies in the stack and is therefore superior to traditional back-side heat removal. Previous work indicated that pin-fin arrays are ideally suited as through-silicon-via-compatible heat transfer structures. In addition, four-port fluid-delivery and fluid-guiding structures improve the heat-removal performance for the nonuniform power maps of high-performance microprocessor chip stacks. Accordingly, an extension of the porous-media multi-scale modeling approach is presented as an efficient approach for designing nonuniform heat transfer cavities. A tensor description in combination with a look-up table is proposed to physically describe periodic porous media, such as pin-fin arrays, in detail. Conjugate heat and mass transfer sub-domain modeling is performed with periodic boundary conditions to derive the orientation-d ependent permeability and angle offset between the pressure gradient and the Darcy velocity direction for pin-fin arrays with a pin diameter of 50 m and pitch and height of 100 m. A local permeability minimum at a flow direction of approx. 30° could be identified. At higher velocities, the fluid flow is biased towards the symmetry lines of the pin-fin array. The modeling concept was validated with experimental readings of a nonuniform, double-side-heated single test cavity. The main characteristics of the temperature field with respect to the four-port architecture, the guiding structures, the fluid temperature increase, and the nonuniform power dissipation are predicted correctly. A statistical comparison of power maps with different heat transfer contrast values resulted in a mean accuracy <6% at a maximal standard deviation of 22.2%. Finally, the potential of the four-port architecture for nonuniform power maps with hot spots in the corners was demonstrated.
  • Publication
    Automated test system for in-situ testing of reliability and aging behaviour of thermal interface materials
    ( 2011)
    AboRas, M.
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    Haug, R.
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    Schacht, R.
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    Monory-Plantier, C.
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    May, D.
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    Wunderle, B.
    ;
    Winkler, T.
    ;
    Michel, B.
    Thermal interface materials (TIMs) are widely needed to improve thermal contacts for facilitation heat transfer in electronic packaging, such as that associated with the flow of heat from microprocessor to a heat spreader or a heat sink in a computer. Due to thermal mismatch between these components mechanical strain occur which cause pump-out, cracks or delamination of TIM. In order to qualify the reliability and aging of TIMs, traditional power cycle test is commonly used to detect potential thermal failures. This traditional power cycle test is a time consuming process due to its long heating and cooling time. Therefore a new automated test system for in-situ reliability testing of TIMs is developed and will be presented in this paper. The new test system is designed to be able to analyze the aging and reliability behavior of most common TIMs. The TIMs can be measured in-situ and under real conditions as they are used in real applications.
  • Publication
    Comparative characterization of chip to epoxy interfaces by molecular modeling and contact angle determination
    ( 2011)
    Hölck, O.
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    Bauer, J.
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    Wittler, O.
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    Michel, B.
    ;
    Wunderle, B.
    An investigation of interfacial interaction has been performed between an industry oriented epoxy molding compound Epoxy Phenol Novolac (EPN) and its filled variety EPNF (with silica particles) and a native silicon dioxide layer (SiO2) usually found at chip surfaces. The free surfaces of both solid materials were experimentally analysed by contact angle measurements of three different liquids (water, methylene-iodide (MI) and glycerol). Results are compared to interfacial energies obtained by analysis of the interfaces in bimaterial molecular models, yielding reasonable agreement. A qualitative prediction regarding the influence of water on the interfacial strength between chip and molding compound is attempted.
  • Publication
    Highly integrated advanced power electronic systems for automotive applications
    ( 2010)
    Sommer, J.-P.
    ;
    Hofmann, Th.
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    Neumann, A.
    ;
    Podlasly, A.
    ;
    Michel, B.
    One of the most important challenges in advanced automotive electronics is to manage increasing power within smaller and smaller devices. Further important requirements are system cost reduction and high reliability. Within the VISA project (fully integrated power electronics for automotive, [1]), funded by the German government, new highly integrated packaging technologies are under investigation which cover active as well as passive components. Some essential technological insights will be presented fIrst. Already in the very fIrst design phase, numerical studies by means of fInite element (FE) analyses have been carried out to ensure the desired reliability with respect to thermal and mechanical properties. This way, a pre-optimisation could be performed. Reliable material data are necessary for reproducible numerical results, including anisotropic information for the laminates built in advanced printed circuit boards (PCB), which have been tested in detail. Embeddin g active power components into a PCB, advanced lamination technologies, precise interconnecting, and test have to be managed precisely. As an example, an engine control unit with an embedded Controller (chips size 7.9 × 6.3 mm2 with 231 pins, 85 m pitch) is chosen, and corresponding results from the VISA project are outlined below. Aim is to ensure the circuit topology of an automotive transmission control unit for life time requirements.