Design of an Ultra Low-Power LDO and Reference System for Always-On Audio Intelligence

This thesis presents the design of an ultra low-power Low-Dropout Regulator including a reference system in 22nm FDSOI-technology. The whole design incorporates a BJT-based reference voltage generation within the LDO regulation loop, thereby reducing quiescent current consumption to only 470 nA and providing a remarkably high DC-Power Supply rejection of 83 dB. This performance has been achieved with a single stage error amplifier topology and an NMOS pass transistor. The LDO delivers an output voltage of 800mV and has been designed for an ultra-low power Analog-Frontend drawing less than 2 μA of current. The comparatively low current-drive requirement, combined with a minimum supply voltage of VDD = 1.2V, motivated the use of an NMOS pass transistor, which generally offers higher power-supply rejection. Further design considerations for the reference system and the LDO are presented, followed by a rigorous verification of the design and initial post-layout results.