Prediction of Analog Circuit Sizing Using an Artificial Neural Network

This paper presents a method for predicting the sizing data of an analog circuit meeting a certain performance with the help of a neural network. The performance data for training is given in two ways. First, an executable function represents the target circuit and second, a lookup table (LUT) is generated from an actual design in the design environment. In order to avoid repeatability and to ensure that the model is tested on a wide range of input datasets, three different datasets are generated through both pre-defined and randomized methods. The model is trained targeting high accuracy. The results are compared and show a good prediction accuracy which verifies the efficiency of the method. We believe that when using this approach, initial sizing of circuits will be eased once the performance was sampled at the beginning. This approach does not aim to completely replace the electrical simulation involved in analog design. Reuse-oriented design flows will take advantage of the method by identifying "go" vs. "no-go" scenarios early in the design process.