Fast and Scalable MAGIC-Based Wallace Tree Multiplier for In-Memory Computing

The growing demand for high-performance, realtime computation in data-intensive applications is increasingly constrained by the Von Neumann bottleneck. In-memory computing (IMC), particularly through memristor-based technologies such as Memristor-Aided loGIC (MAGIC), offers a promising solution by enabling logic operations directly within memory arrays. While prior research has demonstrated basic Boolean logic with memristors, arithmetic operations such as multiplication remain latency-bound due to sequential logic execution and inefficient crossbar utilization. This work introduces a scalable and efficient MAGIC-based Wallace Tree multiplier architecture tailored for in-memory computing. By integrating an optimized 3:2 compressor and leveraging a state-of-the-art synthesis-tomicro-operation mapping tool, our approach significantly reduces latency and improves parallelism within memristor crossbars. Experimental evaluations across 4- to 64-bit unsigned Wallace Tree multipliers show consistent improvements in speed and scalability. The proposed architecture presents a practical and fully scalable design for next-generation in-memory arithmetic systems.