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  4. Macro and Micro-Scale Non-Contact Imaging of Electrically Active Extended Defects in 4H-SiC Merged PiN Schottky Diode Devices
 
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2025
Journal Article
Title

Macro and Micro-Scale Non-Contact Imaging of Electrically Active Extended Defects in 4H-SiC Merged PiN Schottky Diode Devices

Abstract
This study presents a novel approach to device yield estimation based on the non-contact, corona-based QUAD (Quality, Uniformity, and Defects) technique for inline defect mapping in SiC epitaxial layers. The approach is applied to a merged PiN Schottky (MPS) diode manufacturing process and is compared to final wafer-level electrical data. A new analysis method for QUAD defect mapping is introduced, incorporating die yield bin maps based on in-die depletion voltage values, allowing for a direct die to die comparison with standard EOL (End of the Line) electrical device testing. The QUAD mapping flow plan includes initial epi-wafers, the EOL wafers with measurement on metalized MPS dies, and the wafers after stripping off the metal. Micro-scale, µQUAD depletion voltage maps resolving individual dies gives further insight into the nature of the device failures. Novel results show processing induced failures associated with defective electrical isolation of diodes. The unique yield-killing effects of clusters of stacking fault triangular defects are evidenced by a catastrophic breakdown voltage collapse and QUAD depletion voltage collapse in clusters of failed dies near the wafer edges. A strong correlation between the inline QUAD bin map results and final failed device maps highlights the potential of QUAD as a practical and powerful inline tool. This technique, achieving a 94% capture of failing MPS dies, offers a complementary approach to UVPL defect imaging, identifying electrical killer-defects and enhancing the yield estimations.
Author(s)
Faisal, Firas
Nexperia
Steller, Nils
Nexperia
Karhu, Robin  orcid-logo
Fraunhofer-Institut für Integrierte Systeme und Bauelementetechnologie IISB  
Kallinger, Birgit  orcid-logo
Fraunhofer-Institut für Integrierte Systeme und Bauelementetechnologie IISB  
Polisski, Gennadi
Semilab Germany GmbH
Wilson, Marshall
Semilab SDI
Savtchouk, Alexandre
Semilab SDI
Gutierrez, Liliana
Semilab SDI
Almeida, Carlos
Semilab SDI
Soto, Cordero
Semilab SDI
Wilson, Bradley
Semilab SDI
Marinskiy, Dmitriy N.
Semilab SDI
Wincukiewicz, A.
Semilab SDI
Łagowski, Jacek J.
Semilab SDI
Journal
IEEE Transactions on Semiconductor Manufacturing  
DOI
10.1109/TSM.2025.3614854
Language
English
Fraunhofer-Institut für Integrierte Systeme und Bauelementetechnologie IISB  
Keyword(s)
  • 4H-SiC

  • CnCV

  • defect mapping

  • device yield

  • MPS diodes

  • triangular defects

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