An Efficient FeFET-Based Compute-In-Memory Macro Readout Inspired by the 3T Pixel Array Cell

This paper proposes an In-Memory Computing (IMC) FeFET-based macro for ÁI acceleration. Central to this concept is the adoption of a novel readout circuit inspired by the proven efficiency of the 3T pixel array cell. Designed in 28 nm GF technology, this circuitry paradigm not only streamlines the readout process but also optimizes the utilization of FeFETs, enabling enhanced computational capabilities within the IMC accelerator. By combining the benefits of FeFET non-volatile memory cells with the efficiency of the 3T pixel cell circuit, the presented macro offers improved performance and efficiency for IMC AI acceleration.