Process-related challenges in the formation of SiO2 layers by chemical vapour deposition for MEMS applications

We investigate the electrical properties and reliability of silicon dioxide (SiO₂) layers deposited using low-pressure tetraethyl orthosilicate (LP-TEOS) and plasma-enhanced tetraethyl orthosilicate (PE-TEOS) methods. Capacitance-voltage (C-V) and current-voltage (I-V) measurements were performed to evaluate dielectric constant variations, leakage currents, and charge trapping mechanisms. The results show that LP-TEOS films exhibit a strong dependence on deposition temperature and gas flow rate, affecting both the flat-band voltage shift and interface state density. A flat-band voltage shift was also observed in PE-TEOS layers under varying deposition conditions, though it was less pronounced than in LP-TEOS. In both LP-TEOS and PE-TEOS layers, a significant concentration of positively charged defects was observed, except in the wafer deposited at 800 °C using the maximum precursor flow rate. Furthermore, stress measurements indicate compressive stress in both deposition methods, with a significant reduction at higher process temperatures. We also analyzed the transport mechanisms in all films and found that hopping conduction and the Poole-Frenkel satisfactorily describes the current–electric field characteristics at low and intermediate electric fields, while Fowler–Nordheim tunneling dominates at high electric fields. These findings provide valuable insights into optimizing TEOS-based SiO2 films for reliable microelectronic and power device applications.