Reliability of AlScN/GaN HEMTs Under Pulsed Measurements and HTRB Step-Stress Tests: Experimental and TCAD Insights

This work investigates the reliability of AlScN/GaN High-Electron-Mobility Transistors (HEMTs) by integrating experimental analyzes with Technology Computer-Aided Design (TCAD) simulations. The study focuses on pulsed I-V measurements and High-Temperature Reverse Bias (HTRB) step-stress tests. The former have been performed under different quiescent conditions highlight short-term transient charge trapping, while the latter reveals long-term threshold voltage (Vth), transconductance (gm), saturation drain current (ID.ss) and gate leakage (IG) shifts. A TCAD model calibrated on experiments is employed to deeply understand the interplay of the different sources of degradation. In pulsed analyzes, iron traps are identified as the primary degradation contributors. In HTRB step-stress regime, trapped charges under the gate at the 2DEG interface are modeled to reproduce the Vth shift, while the decreased gm is mostly ascribed to donor-trap detrapping at the SiN passivation interface. The relative ID.ss[%] shift and IG are used to validate the proposed approach. Such insights also provide a net comparison of the degradation phenomena in AlScN-based HEMTs with respect to AlGaN-based counterparts, paving the way for improved technology and device designs.