Bunch of Wires Interface PHY Design for Multi-Chiplet Systems

With the increase in downscaling the improvement of system performance has been a tough task. To further improve the performance parameter of the system such as low power, high data rates technologies such as Multichip module (MCM), System in package (SiP) and the integration of chips on an active and passive interposer is being used these days. The recently introduced Bunch of wires interface standard for chip to chip communication for short interface interconnects upto 11 mm length can serve the purpose. This paper presents Bunch of wires standard PHY design which consists of first ever implementation of transmitter (TX) and receiver (RX) architecture.