Radiation-hardened HV Bias and Clock Drivers for next-generation CMOS TDI detector

The aim of the development project for a German CMOS-TDI detector was to control the size of the full-well capacity in the vertical shift register as well as to adjust the operating points. For this purpose, two high voltage (HV) ("Clock Driver"and "Bias Driver") ASICs were designed to provide high-voltage clocking and high-voltage readout control signals for the embedded CCD sensor. The project is carried out by the Institute of Space Research (WR) at the Centre for Robotics and Mechatronics of the German Aerospace Center (DLR) in collaboration with the Fraunhofer Institute for Microelectronic Circuits and Systems (IMS) and other partners. The HV Clock Driver provides four separate clock channels as well as four transfer gate and summing well control signals to 36 independent dual supply high voltage outputs with 12V voltage swing. Each output provides a drive current of +/-50 mA and is stable for capacitive loads of up to 0.35 μF. The clock driving capability can be adjusted according to load capacity and the required output slew rate. The HV Bias Driver provides six single-ended HV output eCCD (embedded CCD) control signal channels with 16 V voltage swing and edge speeds < 200 ns for defined loads. To avoid damaging the eCCD, both ASICs are equipped with a power control block that brings down all outputs to a low voltage in case of a sudden power cut. Both ASICs were developed in a 180 nm, 45 V tolerant HV CMOS technology. In the following details regarding the ASICs' architecture and their circuit implementations are presented, along with radiation test results demonstrating robustness against single event latch-up (SEL) up to LET (Linear Energy Transfer) = 60,4 MeVcm2/mg at 60 °C surface temperature and 10 krad (TID).