Characterization of a 5 GHz Frequency Divider for a Cryogenic PLL in 22-nm FDSOI

This work presents a low-power, fully characterized cryogenic CMOS frequency divider (FD) with divide ratio 512 at 5 GHz, implemented in 22 nm FDSOI for quantum control. Forward back-gate biasing enables robust 4 K operation without a cryo-specific PDK. The divider achieves 1.08 ps RMS jitter and –145.5 dBc/Hz phase noise at 100 kHz offset while consuming 450 µW for the core and 800 µW for the buffer at 4 K. Measurements across temperature and bias points reveal body-bias impact on jitter and noise, guiding cryo-CMOS optimization. Compared to prior work, this design offers higher divide ratio, wider temperature range, and compatibility with standard CMOS. Integration within a cryogenic Phase Locked Loop (PLL) confirms system-level functionality and suitability for scalable, energy-efficient quantum systems.