A Fast Reading Method for Multi-Level RRAM in Small-Scale Arrays

Resistive Random-Access Memory (RRAM) has gained significant interest due to its promising features such as scalability, non-volatility, and multi-level storage capability. This work presents a high-speed reading method employing three parallel Strong-Arm latch comparators operating within a single clock cycle. The proposed approach uses resistor-based reference net and all resistance levels of the one-transistor one-resistor (1T1R) RRAM can be read within 6ns, with a total read power consumption of 61.3µW. The design is well-suited for small-scale RRAM arrays and crossbar architectures, offering a fast and low-power solution.