Transient Simulation of CDM Currents in a Multichip Module Based on Measurements and 3D FEM Simulations

This study presents a methodology for assessing stress currents in multi-chip modules (MCM) during a CDM stress event. The relevant capacitances of the individual chips in a CDM test environment are obtained through FEM simulations and compared with corresponding experimental measurements. Additionally, a package model is developed using further pulsed measurements, enabling circuit simulations of the internal currents flowing between the individual chips.