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  4. Bin-VBSR: Variable Block Size Binned Block-Compressed Sparse Row for Efficient GPU-Accelerated Finite Element Analysis
 
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2025
Conference Paper
Title

Bin-VBSR: Variable Block Size Binned Block-Compressed Sparse Row for Efficient GPU-Accelerated Finite Element Analysis

Abstract
We present Binned Variable Block Compressed Sparse Row (Bin-VBSR), a novel GPU-optimized sparse matrix data structure and associated sparse matrix-vector multiplication algorithm for matrices with variable-size dense blocks. This includes a novel approach to handling long rows in the Binned Compressed Sparse Row (Bin-CSR) family of GPU-optimized sparse matrix data structures. We demonstrate speedups of up to 9.9× over Bin-BCSR* and extend its data compression advantages over compressed sparse row (CSR) to variable block size, resulting in an improvement of up to 50%.
Author(s)
Pfeil, Florian
Fraunhofer-Institut für Graphische Datenverarbeitung IGD  
Ferreira, Stephanie
Fraunhofer-Institut für Graphische Datenverarbeitung IGD  
Mueller-Roemer, Johannes Sebastian  orcid-logo
Fraunhofer-Institut für Graphische Datenverarbeitung IGD  
Mainwork
VMV 2025, Vision, Modeling, and Visualization  
Conference
International Symposium on Vision, Modeling, and Visualization 2025  
Open Access
File(s)
Download (1005.5 KB)
Rights
CC BY 4.0: Creative Commons Attribution
DOI
10.2312/vmv.20251245
10.24406/publica-5573
Language
English
Fraunhofer-Institut für Graphische Datenverarbeitung IGD  
Keyword(s)
  • Branche: Manufacturing and Mobility

  • Research Line: (Interactive) simulation (SIM)

  • LTA: Machine intelligence, algorithms, and data structures (incl. semantics)

  • Matrix representation

  • General Purpose Computation on Graphics Processing Unit (GPGPU)

  • Parallel algorithms

  • FEM Simulation

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