SmartSiC™ 150 & 200mm engineered substrate: increasing SiC power device current density up to 30%

The Smart Cut™ technology enables the integration of high quality SiC layer transfer for device yield optimization, combined with a low resistivity handle wafer (below 5mOhm.cm) to lower device conduction and/or switching losses both for 150mm and 200mm wafers diameter. Based on material characterisation, we anticipate a benefit of up to 15% or 30% in terms of RDSon for state of the art 1200V SiC MOSFET and JFET. 1200V SiC diodes and MOSFETs have been fabricated by Fraunhofer IISB. 1200V diodes (JBS and MPS) with voltage drop improvement by 12% at rated current have been demonstrated. Lowering of the development of SSF is demonstrated after UV illumination opening the path for robustness to bipolar degradation.