• English
  • Deutsch
  • Log In
    Password Login
    Research Outputs
    Fundings & Projects
    Researchers
    Institutes
    Statistics
Repository logo
Fraunhofer-Gesellschaft
  1. Home
  2. Fraunhofer-Gesellschaft
  3. Patente
  4. Voltage reference circuit, integrated circuit, and method for generating a reference voltage
 
  • Details
Options
Patent
Title

Voltage reference circuit, integrated circuit, and method for generating a reference voltage

Other Title
Spannungsreferenzschaltung, integrierte Schaltung und Verfahren zur Erzeugung einer Referenzspannung
Abstract
A voltage reference circuit (1) comprises a first asymmetric differential amplifier (10) and a second asymmetric differential amplifier (20), each comprising two transistors (M1, M2; M1', M2') with different threshold voltages (Vth1, Vth2) as differential pair, a resistor string (30) arranged between an output (13) of the first asymmetric differential amplifier (10) and a supply terminal (VSS), the resistor string (30) comprising a first portion (R1, R2), a second portion (R3, R4) and a connecting circuit node (31) interposed between them, wherein an output (23) of the second asymmetric differential amplifier (20) is coupled to the connecting circuit node (31). The first portion (R1, R2) of the resistor string (30) is configured to provide a first feedback voltage (Vf1) that is fed back to input terminals (11, 12) of the first asymmetric differential amplifier (10), and the second portion (R3, R4) of the resistor string (30) is configured to provide a second feedback voltage (Vf2) that is fed back to input terminals (21, 22) of the second asymmetric differential amplifier (20). The voltage reference circuit (1) is configured to provide a reference voltage (Vref) at the output (13, 23) of the first (10) or the second asymmetric differential amplifier (20).
Inventor(s)
Eberlein, Matthias  
Fraunhofer-Einrichtung für Mikrosysteme und Festkörper-Technologien EMFT  
Link to:
Espacenet
Patent Number
EP4550080 A1
Publication Date
May 7, 2025
Language
English
Fraunhofer-Institut für Elektronische Mikrosysteme und Festkörper-Technologien EMFT  
  • Cookie settings
  • Imprint
  • Privacy policy
  • Api
  • Contact
© 2024