Layout-aware Circuit Sizing using Generators, EAD-based PEX and ADE-based Optimization

The cycle of schematic-level design and post-layout optimization can easily reach ten and more iterations if handled entirely separately. Due to the still mostly manual layout design approach to reach parasitic extraction (PEX), the overall IP design time is often lengthy. In order to investigate parasitic effects early in the design phase for better design optimization, we utilized three EDA tools in our flow. First, layout building blocks are generated by an in-house tool. Second, we used the EAD features to quickly extract the most relevant parasitic effects. Third, we fed the effects back into the schematic-level design and optimized the circuit in ADE with the parasitic effects included – the layout-aware loop closes and is significantly accelerated.
Using this flow, we investigated and compared different design and optimization approaches: pure schematic-level optimization followed by layout design vs. schematic-level optimization with the EAD-based PEX included vs. a mixture of both. The results show that the early consideration of parasitic effects allows the optimizer to find a better circuit sizing in the sense that it is much more robust against the (additional) layout effects. In future, AI-based models might further support this flow by even faster estimation of parasitics right from the schematic.