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  4. A Reading Method for 2T2R RRAM Arrays Coding their Multiple States
 
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August 11, 2024
Conference Paper
Title

A Reading Method for 2T2R RRAM Arrays Coding their Multiple States

Abstract
Resistive random-access memory (RRAM) devices have been frequently mentioned considering their robust performances. The conventional transistor one-memristor (1TIR) RRAM device becomes less competitive considering its multi- level operation. This paper introduces a two-transistor two- memristor (2T2 R) structure as well as a reading method for the configuration. The designed sense circuit based on a Strong-Arm latch codes 9 different states with 6 bits in 48ns and consumes a power of 7.6uW and it also demonstrates a tolerance to RRAM technologies and variations.
Author(s)
Guo, Running
Pechmann, Stefan
Hagelauer, Amelie  
Fraunhofer-Einrichtung für Mikrosysteme und Festkörper-Technologien EMFT  
Mainwork
IEEE 67th International Midwest Symposium on Circuits and Systems, MWSCAS 2024  
Conference
International Midwest Symposium on Circuits and Systems 2024  
DOI
10.1109/MWSCAS60917.2024.10658733
Language
English
Fraunhofer-Einrichtung für Mikrosysteme und Festkörper-Technologien EMFT  
Keyword(s)
  • 1TIR

  • 2T2R

  • RRAM device

  • Strong-Arm latch

  • multi-level

  • reading method

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