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  4. A ΣΔ-Modulated Linear-in-dB Attenuator for On-Chip Power Detection with 0.12 dB Resolution in RF SOI CMOS Switch Technology
 
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June 16, 2024
Conference Paper
Title

A ΣΔ-Modulated Linear-in-dB Attenuator for On-Chip Power Detection with 0.12 dB Resolution in RF SOI CMOS Switch Technology

Abstract
In this work, an innovative scheme to boost the resolution of the variable radio-frequency (RF) attenuator is proposed and examined. The attenuator stage modulated by a first-order sigma-delta modulator (ΣΔM) shows a linear-in-dB attenuation profile for the average RF power with high resolution. The proposed attenuator provides a low-power solution for accurate on-chip power measurement with zero quiescent current. The implemented attenuator shows an effective attenuation tuning step size of 0.12 dB from 700 MHz to 6 GHz with a power consumption of only 41.4 μW. The device is designed and fabricated in 90 nm RF SOI CMOS switch technology.
Author(s)
Hsu, Ting-Li
Solomko, Valentyn
Hagelauer, Amelie  
Fraunhofer-Einrichtung für Mikrosysteme und Festkörper-Technologien EMFT  
Mainwork
IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2024  
Conference
Radio Frequency Integrated Circuits Symposium 2024  
DOI
10.1109/RFIC61187.2024.10600013
Language
English
Fraunhofer-Einrichtung für Mikrosysteme und Festkörper-Technologien EMFT  
Keyword(s)
  • attenuator

  • CMOS attenuator

  • sub-6 GHz

  • variable attenuator

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