Microcracking in On-Chip Interconnect Stacks: FEM Simulation and Concept for Fatigue Test

The semiconductor industry is continuing the scaling down of both device and on-chip interconnect features, for performance and economic reasons. This trend has implications for the design of guard ring structures, i.e. metallic non-functional structures in the back-end-of-line (BEoL) stack designed to be efficient to stop microcracks. In this work, we present a sample design for an in situ experiment to study mechanical degradation and failure mechanisms of crack stop structures in the BEoL stack, to ensure the mechanical robustness of microchips for future technology nodes. Additional finite element method (FEM) simulations provide supplementary understanding of the crack kinetics. To examine the effects of mechanical loading on crack stop elements of the BEoL stack, a novel sample geometry for an in situ fatigue experiment using x-ray microscopy was developed. The x-ray microscope (ZEISS Xradia 800 Ultra) enables high-resolution imaging of the 3D-patterned sample structures and defects such as microcracks. The tailored sample geometry allows the application of a tensile load to a BEoL specimen by a lever mechanism. The feasibility of the sample design is shown by mode-I loading of a pure interconnect sample. Post-mortem analysis by scanning electron microscopy (SEM), confirming planar microcrack propagation from the notch through the dielectric layer with small deflections of the crack path near cone shaped copper vias. FEM simulations focusing on the stress-strain fields around a crack tip indicate the beginning of copper plasticity as major mechanism starting the redirection of cracks due to resulting material compression in front of the obstacle.