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  4. Multi-Level Programming on Radiation-Hard 1T1R Memristive Devices for In-Memory Computing
 
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2023
Conference Paper
Title

Multi-Level Programming on Radiation-Hard 1T1R Memristive Devices for In-Memory Computing

Abstract
This work presents a quasi-static electrical characterization of 1-transistor-1-resistor memristive structures designed following hardness-by-design techniques integrated in the CMOS fabrication process to assure multi-level capabilities in harsh radiation environments. Modulating the gate voltage of the enclosed layout transistor connected in series with the memristive device, it was possible to achieve excellent switching capabilities from a single high resistance state to a total of eight different low resistance states (more than 3 bits). Thus, the fabricated devices are suitable for their integration in larger in-memory computing systems and in multi-level memory applications.
Author(s)
Perez-Bosch Quesada, Emilio
Rizzi, Tommaso
Gupta, Aditya
Mahadevaiah, Mamathamba K.
Schubert, Andreas
Pechmann, Stefan
Jia, Ruolan
Uhlmann, Max
Hagelauer, Amelie  
Fraunhofer-Einrichtung für Mikrosysteme und Festkörper-Technologien EMFT  
Wenger, Christian
Perez, Eduardo
Mainwork
14th Spanish Conference on Electron Devices, CDE 2023. Proceedings  
Conference
Spanish Conference on Electron Devices 2023  
DOI
10.1109/CDE58627.2023.10339525
Language
English
Fraunhofer-Einrichtung für Mikrosysteme und Festkörper-Technologien EMFT  
Keyword(s)
  • Resistance

  • Layout

  • Voltage

  • Programming

  • Logic gates

  • in-memory computing

  • CMOS technology

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