TCAD modeling and simulation of self-limiting oxide growth and boron segregation during vertical silicon nanowire processing

Thermal oxidation is a key step for the fabrication of vertical gate-all-around nanowire field-effect transistors (GAA-NW-FETs). It is used after the etching of nanopillars from the silicon substrate to further thin the nanowire diameter, remove the etching damage and have good control of the geometry. It can also be used to grow a gate oxide. Thermal oxidation of silicon nanowires is a self-limiting process. Self-limiting effects, which are due to the mechanical stress in the structure, need to be accurately modeled to obtain predictive simulations of nanowire geometry, and so of the GAA-NW-FET channel dimensions, after thermal oxidation. Moreover, boron segregation during thermal oxidation into the growing oxide results in a considerable dopant loss from the nanowire. Correct modeling of such effects is also paramount for the investigation and simulation of the electrical characteristics of nanowire transistors, especially for p-type junctionless GAA-NW-FETs. In this work, we present a comparison of 2D and 3D TCAD process simulations of the oxidation of silicon nanowires with experimental data. Based on that, we suggest novel sets of calibrated parameters for stress-dependent oxidation, relevant particularly for nanowire diameters below 60 nm, and for boron segregation.