Advanced Physical Analysis of Integrated Circuits for Tampering Detection

As parts of the IC production, e. g. design and manufacturing, are distributed worldwide this supply chain is vulnerable for malicious attacks at certain points. Such attacks include unwanted modifications of the design and IC hardware like insertion of HW trojans as well as the exchange of the IC devices with counterfeits in the final product. Due to such threats occurring more and more in the past methods to check the authenticity of existing semiconductor products for security assurance are highly necessary.
In case of hardware modifications hidden inside the IC across its whole 3D assembly the ability for full layer-by-layer reverse engineering of integrated circuits is key for their successful detection which finally achieves trust in critical devices from global supply chains. This RE flow includes the analysis and deprocessing of the chip combined with highly precise imaging by means of electron and ion beam chip scanning for final layout extraction and comparison with the original IC design.
While the feature sizes of ICs shrink to few nanometers the thickness of layers is reduced to some ten nanometers. One challenge of tackling physical and technical limits is to achieve homogeneity across several mm chip dimensions as a prerequisite for further full-chip imaging.
In our talk we present today’s methods and preparation results from our CC-EAL6 certified analysis lab for chip technologies down to 7 nm.