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  4. A DC SPICE Level 3 Model for 4H-SiC lateral NMOSFET under strong inversion conditions
 
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2023
Conference Paper
Title

A DC SPICE Level 3 Model for 4H-SiC lateral NMOSFET under strong inversion conditions

Abstract
A DC SPICE model of a 4H-Silicon Carbide lateral n-type Metal Oxide Semiconductor Field Effect Transistors is proposed. Basing on a SPICE MOSFET Level 3 model, we introduce a novel equation of the threshold voltage, because its classic description is invalid due to the high density of traps at the oxide/semiconductor interface. Moreover, we also consider the body effects on the threshold voltage and on the channel mobility as well as the high-field effects. The accuracy of our model has been verified through the comparisons with experimental data and the relative Verilog-A BSIM4SiC model. The devices are fabricated with the 2μm CMOS process by Fraunhofer IISB and have channel length and width of 10μm. The output and trans-characteristics are for room temperature and under different bias conditions of the drain, gate and body terminals.
Author(s)
Rinaldi, Nicola
Licciardo, Gian Domenico
Benedetto, Luigi di
Rommel, Mathias  orcid-logo
Fraunhofer-Institut für Integrierte Systeme und Bauelementetechnologie IISB  
Erlbacher, Tobias  
Fraunhofer-Institut für Integrierte Systeme und Bauelementetechnologie IISB  
Mainwork
PRIME 2023, 18th International Conference on PhD Research in Microelectronics and Electronics. Conference Proceedings  
Conference
International Conference on PhD Research in Microelectronics and Electronics 2023  
DOI
10.1109/PRIME58259.2023.10161965
Language
English
Fraunhofer-Institut für Integrierte Systeme und Bauelementetechnologie IISB  
Keyword(s)
  • 4H-SiC lateral MOSFET

  • electrical characteristics

  • SPICE model

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