Surrogate-Based Modeling Techniques for Mapping Transistor Figures of Merit onto Compact Model Parameters

The electrical characteristics of a transistor can deviate from its nominal behavior due to process variations, aging mechanisms, etc. In order to ensure the reliability of a design, circuit level simulations capturing this altered transistor behaviors have become increasingly important. In this paper we study the use of surrogate models to map changes in key transistor's figures of merit into compact model parameters in order to shorten the path from reliability measurements to simulations.