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  4. GaN-HEMT with a Back-Gated Segment for High Voltage Cascodes
 
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2023
Conference Paper
Title

GaN-HEMT with a Back-Gated Segment for High Voltage Cascodes

Abstract
This work presents the design, fabrication, and measurements of a GaN-HEMT with a back-gated segment and pull-down pin in a GaN-on-Si technology. The device is designed for the use in high voltage cascodes. The static and dynamic characteristics of the device is demonstrated in a three-stage hybrid cascode assembly. The cascode was measured with a blocking voltage up to 1250 V.
Author(s)
Reiner, Richard  
Fraunhofer-Institut für Angewandte Festkörperphysik IAF  
Mönch, Stefan  orcid-logo
Fraunhofer-Institut für Angewandte Festkörperphysik IAF  
Waltereit, Patrick  
Fraunhofer-Institut für Angewandte Festkörperphysik IAF  
Basler, Michael  
Fraunhofer-Institut für Angewandte Festkörperphysik IAF  
Müller, Stefan
Fraunhofer-Institut für Angewandte Festkörperphysik IAF  
Mikulla, Michael  
Fraunhofer-Institut für Angewandte Festkörperphysik IAF  
Quay, Rüdiger  orcid-logo
Fraunhofer-Institut für Angewandte Festkörperphysik IAF  
Mainwork
IEEE 35th International Symposium on Power Semiconductor Devices and ICs, ISPSD 2023  
Conference
International Symposium on Power Semiconductor Devices and ICs 2023  
DOI
10.1109/ISPSD57135.2023.10147630
Language
English
Fraunhofer-Institut für Angewandte Festkörperphysik IAF  
Keyword(s)
  • GaN-on-Si

  • cascodes

  • cascades

  • stacking

  • back-gating

  • self-compatible transistor

  • multi-stage transistor circuit

  • Fraunhofer-Leitprojekt ElKaWe

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