Non-parasitic induced transient overvoltage in ANPC topology due to critical switching sequences

This paper describes a semiconductor overvoltage in an Active-Neutral-Point-Clamped Converter (ANPC). This overvoltage occurs in case of inductive load when the output voltage of the ANPC changes its polarity. In case of a grid inverter this occurs twice per grid period at the voltage zero crossing. It can be observed in most of the ANPC-based power electronics with classical PWM patterns and can reach the full DC-Link voltage. Although the ANPC is a well-known and widely spread topology there has been no particular concern in literature about this effect yet. From our point of view, the reason for this is a generous semiconductor dimensioning in terms of blocking voltage utilization and the limited energy due to the nature of the overvoltage. Nevertheless, this overvoltage could become a problem in modern designs when SiC MOSFETs are used, and their Safe Operating Areas (SOA) are pushed even further to the limits. The shown overvoltage is not a switching overshoot due to parasitic inductances and high switching speeds. It cannot be explained by "hazardous" switching states either. In the following, the emergence is described in detail and a theoretical model is introduced and evaluated by simulations and measurements. Afterwards, methods to avoid the overvoltage are shown and a risk estimation is performed.