Benchmarking experiment of substrate quality including SmartSiC™ wafers by epitaxy in a batch reactor

To produce Silicon Carbide (4H-SiC) power electronic devices, conventional 4H-SiC substrates with 150 mm diameter and 350 µm thickness are currently widely used, which can be purchased from many vendors worldwide. Today, they are still an essential part in the cost structure of power electronic devices as the production of such 4H-SiC is expensive. Moreover, today's SiC substrates contain structural defects, which are inherited to the epilayer and hence, the active device area, where they can limit the device performance and production yield. Using a very thin 4H-SiC layer could be sufficient for epitaxy and device production and the defectivity of the epilayer could also be improved. In addition, the device performance can be strongly enhanced thanks to lower device conduction and/or switching losses using ultra high conductivity receiver substrates. SOITEC's Smart Cut™ process [1] yields such a 0.6 µm thin SiC layer, which is transferred to a polycrystalline SiC carrier substrate and bonded thanks to a conductive bonding, called SmartSiC TM substrate. Defects in epilayers on such SmartSiC™ substrates can then have three different origins: 1) inherited from the conventional substrate, 2) originate from the Smart Cut™ and layer bonding processes, and 3) originate from the epi growth itself. This paper aims to investigate the current quality of epilayers grown on SmartSiC™ substrates and identify the origin of defects. Therefore, SmartSiC™ and conventional 4H-SiC substrates are benchmarked in a comprehensive epitaxial study in the framework of the TRANSFORM EU project. The benchmark study comprises SmartSiC™ substrates of 4H-SiC donor wafer bonded onto 4H-SiC handler (in this paper named Gen1.1), 4H-SiC bonded onto poly-SiC (in this paper named Gen1.2) and conventional substrates from STMicroelectronics as partners in the TRANSFORM project as well as other international suppliers (vendor A with prime and engineering grade, vendor B with prime grade). All substrates are n-type and 150 mm in diameter. All SmartSiC™ substrates contain a conductive bonding layer, the Gen 1.1 substrates a monocrystalline 4H-SiC carrier wafer and the Gen 1.2 a polycrystalline SiC carrier wafer. The SiC top layers of the SmartSiC™ substrates compare well to the conventional substrates provided by STMicroelectronics, hence, we can conclude which defects in the epilayer originate from the substrate material. To investigate if the Smart Cut™ process introduces additional defects to the epilayer and if the epi growth process needs further optimization for SmartSiC™ substrates, conventional substrates from different international suppliers are added. All prime grade non SmartSiC™ substrates have been characterized prior to epi growth by x-ray topography (XRT) with a Rigaku XRTmicron [2] and all have been measured with UVPL imaging and surface inspection with a Lasertec SICA88 and Intego AQUILA systems. Then, a sequence of epi growth runs has been started in an AIXTRON G5 WW C planetary reactor in 8x150 mm configuration: 1) a standard epi growth process including buffer growth and standard epilayer; 2) a buffer only growth; and 3) a heat-up and cool-down procedure with thermal etching at process temperature. During the epitaxial growth process in-situ data of temperature profiles and wafer curvature was recorded. All wafers with grown layers were then characterized regarding epilayer thickness and doping concentrations by FTIR spectrometry and mercury probe CV measurements, respectively. All wafers are being characterized using UVPL imaging plus DIC/optical microscopy and all full stack epilayers with XRT for defectivity after the epitaxial process or thermal etching. The epi growth results for the epilayer thickness and doping are summarized in Table I. Due to the large batch capacity of the used epitaxy reactor all different types of substrates could be processed in the same run. First in-situ measurements showed a typical concave wafer curvature in process of 50-80 km-1 for the reference wafers from international suppliers A and B as well as for the SmartSiC™ Gen 1.1 substrates. The substrates supplied by STMicroelectronics showed slightly lower curvature values in the range around 35 km-1. The Gen 1.2 substrates (on the polycrystalline carrier) showed a convex curvature of approximately -40 km-1.
When characterized for defects on a Lasertec SICA88 we found all epilayers and buffer structures being very similar in numbers of triangles and stacking faults with a surface signal (Fig. 1-3). The engineering grade wafers of vendor A showed a larger density of basal plane dislocations in the epilayer whereas all prime grade substrates and the SmartSiC™ substrates showed a low density with little difference between substrate suppliers. The prime grade wafers by STMicroelectronics, which are also to be used as the donor for the SmartSiC substrates in some cases, had a lower density of micropit features on the grown epilayer. Some features of triangle defects visible only in the PL channel of the defect scanning system are seen on the SmartSiC™ substrates and will be more deeply analyzed after XRT measurement.
Further studies about the origin of these differences will be conducted using additional XRT measurement on the epilayers and by using a second defect map generated with the Intego AQUILA system on all processed wafers. So far, the SmartSiC™ substrates perform similar to standard prime grade wafers from reference suppliers.