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  4. Tilt- and warpage measurement as inline quality assessment tool
 
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2022
Journal Article
Title

Tilt- and warpage measurement as inline quality assessment tool

Abstract
The tilt of semiconductor dies is a common issue during assembly in power electronics as, e.g. die bonding during silver sintering caused by inhomogeneous thicknesses of applied die-attach material, problems with a homogeneous force application, uneven substrates etc. This tilt usually leads to reliability problems later during testing or operation in the field. A weakly sintered layer will be formed with voids larger than 1-2 μm in major numbers and more importantly will lead to insignificantly developed interfaces. None of them can be detected by SoA failure analytical techniques like scanning acoustic microscopy (SAM) or pulsed infrared thermography (PIRT), since both will still provide a sufficient phonon coupling, indistinguishable to well sintered layers. However, the undetected weak interfaces will lead to severe reliability problems and can only be detected indirectly by thickness measurement without a cross section. In this work, we present a scanning system based on confocal polychromatic distance sensors, which can scan a fully loaded tray of bonded dies on the substrate for industry-grade inline integration. We demonstrate the novel system on different bonded power dies on active metal braze substrate (AMB) under industrial production conditions. We achieve this in the required accuracy of about 2-3 μm in an environment with strong vibration influence. The in-line capability has been proven by using a setup, which is independent of mechanical vibrations and uses only optical fibers to transfer measuring signals within future smart production environments.
Author(s)
May, D.
Technische Universität Chemnitz  
Heilmann, J.
Technische Universität Chemnitz  
Boschman, E.
Boschman Advanced Packaging Technologies
Abo Ras, M.
Berliner Nanotest und Design GmbH
Wunderle, Bernhard  
Technische Universität Chemnitz  
Journal
Microelectronics reliability  
DOI
10.1016/j.microrel.2022.114601
Language
English
Fraunhofer-Institut für Elektronische Nanosysteme ENAS  
Keyword(s)
  • 100 % inspection

  • Chip

  • Inline testing

  • Quality assessment

  • Tilt

  • Warpage

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