CMOS-compatible fabrication of perforated membranes for filtration applications

We report the development and successful implementation of a new process for manufacturing thin (< 1 µm) horizontal membranes with submicron holes on silicon chips for applications such as filtration, detection and/or separation of cells. Most of the currently available methods for manufacturing similar devices are not compatible with CMOS technology. The process proposed here, by contrast, combines standard i-line stepper lithography with (deep) reactive ion etching, ion beam etching and atomic layer deposition, allowing for a CMOS compatible fabrication. As the process exclusively uses standard microsystems technology operations on 200 mm silicon wafers it is also suitable for mass production. Moreover, the geometric parameters - including thickness/diameter, number, location and spacing of membranes, cavities and holes - are clearly defined and adjustable to the requirements of the different applications mentioned above. Scanning electron microscopy proved the successful creation of a stable membrane and the establishment of a connection between front and backside of the chips. In total, this may allow for a future integration of electrical functionalities into the chip, opening up new possibilities for further applications of the perforated membranes.