System Level ESD Testing with Capacitively Coupled Stress Pulses

A debugging test method is presented which helps to identify susceptible pins which failed after system level ESD testing in compliance with IEC 61000-4-2. It applies capacitive coupling between the test probe ground plane (GP) and a chip of an operated equipment under test (EUT) to provide a return path for a stress pulse generated by a transmission line pulsing (TLP) pulse generator. The voltage pulse is injected into a single pin of a tested device within an EUT, which allows to evaluate the susceptibility to ESD induced failures for each pin of an operated EUT in a time and cost-effective manner.