A Read Circuit Design for Multi-Level RRAM Cells Exhibiting Small Resistance Windows

Memory integration is a key issue for emerging memory technologies. In order to properly integrate a novel memory technology, precise and reliable read circuits and concepts are necessary. But especially in emerging technologies, the electrical properties of the individual cells can vary widely, demanding additional flexibility. The presented circuit design offers a read circuit for RRAM cells based on voltage evaluation, that is able to resolve very small resistance ratios of up to 1.31 while offering multi-level capability. By changing some circuit parameters, it can be adopted to different given electrical properties.