Cylindrical indentation to selectively stress nanoscale CMOS transistors

Advanced indentation techniques have been introduced to study the effects of multiple stresses on the transistor characteristics with using a cylindrical tip with various alignments. Particularly, controlling the cylinder tip orientation relative to the transistor channel direction is proposed to selectively strain the silicon channels in order to induce very different selectively controlled stresses. Several tip alignments allow to shift the stresses from uniaxial towards biaxial stress as well as to induce shear stress. Ring oscillator circuits based on NAND and NOR gates are used to monitor the stress effects on the characteristic circuit frequency as well as on the individual transistors. Finite Element simulations help to identify optimized setup properties for the targeted application. Comparison with previous indentation experiments derives the specific influence of each stress tensor component on the transistor characteristics.