Development of an analog front-end for brain-computer interfaces

In the context of the development of an implantable embedded system interfacing brain activity and enabling paralyzed patients to interact with devices that are usable on an everyday basis, we designed a real-time-suitable, low-power hardware architecture with an artifact-suppressing analog front-end, connected to a neural signal processing pipeline. As part of the ultra low-noise analog front-end (four-channel), the common average referencing (CAR) algorithm is implemented to reduce spurious signals from the environment by recording the adjacent electrodes of an invasive microelectrode array (MEA). A Field-Programmable Gate Array (FPGA) is used for data acquisition of extracellular spike activity and data transmission via Ethernet to a host computer for external processing of neural signals. The presented prototype achieves an SNR of 38 dB by applying spike inputs with amplitudes of 100 μV using commercially available components.