Design and Characterization of an Interleaved GaN Half-Bridge IC with Matrix Layout

This work investigates the design and characterization of an interleaved GaN half-bridge IC with a matrix layout for low-voltage applications. The work provides an understanding for the interleaved half-bridge design and it derives design equations from a distributed resistive element model. The area-specific onstate resistance is analyzed as a function of design and technology parameters. Practical aspects of conventional assembly technologies are considered. Furthermore, a new three-dimensional fractal design for large and area-efficient modules is presented. A fabricated power IC device demonstrator includes three independent normally-off half-bridge phases on a total chip area of 2×2 mm². Each of the six half-bridge transistors features a low on-state resistance of RON = 110 mΩ and a measured off-state voltage of 60 V.