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  4. Evaluating the feasibility of a RISC-V core for real-time applications using a virtual prototype
 
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February 28, 2022
Presentation
Title

Evaluating the feasibility of a RISC-V core for real-time applications using a virtual prototype

Title Supplement
Conference paper at Design and Verification Conference and Exhibition. United States 2022, 28.02.2022 - 03.03.2022, San Jose, California
Abstract
The replacement of a key component within industrial embedded systems usually requires huge verification and validation efforts. Especially the replacement of the MCU core architecture normally entails significant changes to the HW/SW co-design and co-verification process, possibly including the purchase of costly design and verification IP. Our intended use-case is a system redesign where an established MCU is replaced by a RISC-V core. Since the complete redesign process requires a significant effort, a feasibility evaluation study helps to elaborate the system requirements and to detect possible issues early in the replacement process. Once feasibility has been demonstrated, hardware (re-)design may start. In this paper we propose a HW/SW co-verification methodology to evaluate the feasibility of an MCU core replacement based on a virtual prototype, thereby saving time and cost for the redesign process. This methodology links the VP development process with the requirements management process to re-use the test cases.
Author(s)
Santana, Juan  
Fraunhofer-Institut für Integrierte Schaltungen IIS, Institutsteil Entwicklung Adaptiver Systeme  
Pachiana, Gabriel  
Fraunhofer-Institut für Integrierte Schaltungen IIS, Institutsteil Entwicklung Adaptiver Systeme  
Markwirth, Thomas  orcid-logo
Fraunhofer-Institut für Integrierte Schaltungen IIS, Institutsteil Entwicklung Adaptiver Systeme  
Sohrmann, Christoph  
Fraunhofer-Institut für Integrierte Schaltungen IIS, Institutsteil Entwicklung Adaptiver Systeme  
Fischer, Bernhard
Siemens AG
Matschnig, Martin
Siemens AG  
Project(s)
Verification and Validation of Automated Systems' Safety and Security  
Funder
This project has received funding from the ECSEL Joint Undertaking (JU) under grant agreement No 876852.
Conference
Design and Verification Conference and Exhibition 2022  
Open Access
File(s)
Download (1.04 MB)
Rights
CC BY-NC-ND
DOI
10.24406/publica-125
Language
English
Fraunhofer-Institut für Integrierte Schaltungen IIS  
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