Experimental evaluation of the device design and process technology of the current aperture vertical electron transistor for power electronics applications

GaN-based devices offer great potential for high-power and high-frequency applications. Nevertheless, most investigated lateral high electron mobility transistor (HEMT) structures suffer from high gate-to-drain spacing to sustain high voltage operation. In contrast, vertical device designs offer enhanced area efficiency in the high power region, as the drift region can be scaled independent of the wafer area. The wafer footprint can be drastically reduced, which results in higher power density and reduced cost. In addition, the vertical layout exhibits several additional advantages in terms of device reliability, current density, design-possibilities and packaging. The current aperture vertical electron transistor (CAVET) is a promising candidate for vertical GaN-devices, as it combines the established gate-source module of a lateral HEMT with the benefits of a vertical depletion- and drift-region. In contrast to all other vertical GaN designs, the CAVET offers the possibility to be directly integrated into proven AlGaN/GaN-technology as a high-power switch. The combination of CAVETs and on-chip integrated HEMTs enables the introduction of several new design opportunities for high-functional, monolithically integrated GaN power ICs.
Even though some small area CAVETs were demonstrated by various fabrication strategies, the intrinsic device design, the challenges in the fabrication process and their impact on the performance of the fabricated devices are rarely explored. In addition, although promising results were presented, the fabricated transistors were limited to maximum drain currents in the mA-range and the off-state robustness has so far been an issue in CAVET-technology. Therefore, both parameters need to be improved significantly to demonstrate the suitability of the CAVET-technology for high-power applications. However, to improve the device performance and stability, an improved understanding of the device phyiscs and the influence of the process technology is necessary. The aim of this thesis are CAVETs for power electronics applications by a numerical analysis and an experimental evaluation of the device design and the process technology.
Theoretical modeling of CAVETs was first carried out and discussed, in order to evaluate the impact of the fundamental device design parameters on on-state, transfer and off-state characteristics. Based on the results of the simulations, critical design parameters are elaborated. Large apertures with low donor concentrations and a substantial gate-aperture overlap were shown to be required to derive a robust device layout and reliable gate control to suppress source-drain leakage. Based on the results of the simulations, a suitable layout for the process masks was developed for the following process technology.
A major challenge in the fabrication of CAVET structures has been the diffusion of Mg from the current blocking layer (CBL), which serves as a potential barrier between source and drain, during the overgrowth of the GaN-channel and the AlGaN-barrier. In order to circumvent the need of an industrially unsuitable and expensive molecular beam epitaxy (MBE) regrowth step, two different CAVET fabrication strategies were developed fully based on metalorganic chemical vapor deposition (MOCVD). Current blocking layer formation was carried out by non-planar selective area regrowth or v Mg-ion implantation and its structural evolution was discussed. Subsequently, AlGaN/GaN regrowth is performed by MOCVD and analyzed while focusing on the Mg-distribution into the regrown channel and the influence on the electrical characteristics of the two-dimensional electron gas (2DEG). Structural and electrical characterization of the CAVET structures revealed much better results for CAVETs with Mg-implanted CBL, which was explained by the better surface morphology and the smaller Mg-tail into the regrown GaN-channel. As a result, higher crystal quality and no compensation of the 2DEG was demonstrated for Mg-implanted samples. Reliable 2DEG-performance in SAG-based CAVET structures was only achievable by decreasing the Mg-concentration and increasing the distance of the CBL to the 2DEG. However, based on the TCAD simulations both was expected to degenerate the device performance in terms of turn-off behavior and off-state stability.
Further investigation on the two fabrication strategies was carried out by the measurement of fully processed transistors. The experimentally derived data of the device layout were found to match the trends obtained by TCAD simulations. However, based on the results of the elemental distribution, the structural and electrical characterization as well as the analysis on device level, the fabrication via Mg-implantation provides significantly improved device performance in terms of on-state, transfer and off-state characteristics. Especially, the leakage through the CBL was found to be much lower when compared to SAG-CAVETs, which is assumed to be caused by lower electric field penetration in the CBL due to the higher achievable Mg-doping concentration. In addition, the off-state stability of the Mg-implanted small transistors exceeded the previously demonstrated approaches.
To prove the high-power robustness of the device design in combination with the implantation-based fabrication process, a suitable upscaling pathway of the CAVET-technology was investigated. Large area CAVET comb structures are proposed by combining the optimal intrinsic CAVET design of small transistors, with the proven comb structure of the lateral HEMT. Device characteristics are carried out and compared to the results of small demonstrators from previous chapters. Reliable on-state, transfer and off-state characteristics were shown for the upscaled devices, which further proves the suitability of the developed layout and process technology.
The findings of this work were applied to a component design and have resulted in a CAVET with the largest absolute current of over 20 A, which is an increase by a factor of 103 compared to the state of the art. Simultaneously, the critical field strength in the largest fabricated devices was found to be close to previously shown small gate width devices. The demonstrated pulse power stability of nearly 1 kW is close to the theoretical for lateral HEMTs, which demonstrates, that the CAVET-technology is suitable for the use in power electronics. In addition, the developed technology allows for the fabrication of CAVETs with co-integrated lateral HEMTs on-chip, which enables the monolithic integration of conventional gate drivers and sensor systems into the CAVET-technology.